Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times

Patent metadata

Field	Value
Publication number	US-9261940-B2
Application number	US-201213396618-A
Country	US
Kind code	B2
Filing date	Feb 15, 2012
Priority date	Feb 25, 2011
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

First claim

What is claimed is:

1. A memory system comprising a plurality of memory devices and a controller, each of the memory devices comprising:
an internal clock generator that generates an internal clock in synchronization with a processor clock received from the controller, in response to the processor clock; and
a memory that performs a peak current generation operation within a peak current generation period in synchronization with the internal clock,
wherein two or more of the memory devices generate their respective internal clocks at different times, and
wherein the controller monitors a peak signal transmitted from the plurality of memory devices and activates the processor clock differently in response to the peak signal.

2. The memory system of claim 1 , wherein the respective internal clocks of the memory devices are activated at different edges of the processor clock.

3. The memory system of claim 1 , wherein the respective internal clocks of all of the memory devices are activated at different times with respect to the same processor clock.

4. The memory system of claim 1 , wherein the processor clock has a cycle time corresponding to the peak current generation period, and wherein the memory devices are sequentially activated at corresponding edges of the processor clock.

5. The memory system of claim 1 , wherein the internal clocks of first and second memory devices among the memory devices are simultaneously activated.

6. The memory system of claim 1 , wherein the peak current generation period is set differently according to a type of operation performed by the memory.

7. The memory system of claim 6 , wherein the peak current generation period is set to correspond to at least one of a bitline setup period for programming data in the memory and a bitline precharge period for verifying the programmed data.

8. A memory system comprising a plurality of memory devices and a controller, each of the memory devices comprising:
an internal clock generator that generates an internal clock in synchronization with a processor clock received from the controller, in response to the processor clock;
a memory that performs a peak current generation operation within a peak current generation period in synchronization with the internal clock,
wherein two or more of the memory devices generate their respective internal clocks at different times; and
a timer for counting time passed from a first time, wherein the period of the peak current generation operation is set differently according to the time passed from the first time,
wherein the controller monitors a peak signal transmitted from the plurality of memory devices and activates the processor clock differently in response to the peak signal.

9. A memory system comprising a plurality of memory devices and a controller, each of the memory devices comprising:
an internal clock generator that generates an internal clock in synchronization with a processor clock received from the controller, in response to the processor clock;
a memory that performs a peak current generation operation within a peak current generation period in synchronization with the internal clock,
wherein two or more of the memory devices generate their respective internal clocks at different times; and
a counter for counting a number of times that a first operation is repeated, wherein the peak current generation period is set according to the number of times that the first operation is repeated,
wherein the controller monitors a peak signal transmitted from the plurality of memory devices and activates the processor clock differently in response to the peak signal.

10. The memory system of claim 1 , wherein the peak current generation period of a first memory device among the memory devices is set differently from the peak current generation period of a second memory device.

Assignees

• Kim Bo-Geun
• Kyung Kye-Hyun
• Jeong Jae-Yong
• Choi Seung-Hun
• Kwon Seok-Cheon
• Lee Chul-Ho
• Samsung Electronics Co Ltd

Inventors

• Kim Bo-Geun
• Kyung Kye-Hyun
• Jeong Jae-Yong
• Choi Seung-Hun
• Kwon Seok-Cheon
• Lee Chul-Ho

Classifications

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title