Phase detector

Patent metadata

Field	Value
Publication number	US-9258110-B2
Application number	US-201414266785-A
Country	US
Kind code	B2
Filing date	Apr 30, 2014
Priority date	Apr 30, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.

First claim

What is claimed is:

1. A device comprising a phase detector, the phase detector comprising:
a frequency information input;
a phase information input;
an adder, the frequency information input being coupled with a first input of the adder and the phase information input being coupled with a second input of the adder; and
a modulo operation coupled between the frequency information input and the first input of the adder, wherein the modulo operation is an operation which outputs a rest of a division by N.

2. The device of claim 1 , wherein the modulo operation is operative in a first mode of operation of the phase detector and non-operative in a second mode of operation of the phase detector, the device further comprising a frequency control word accumulator, an output of the frequency control word accumulator being coupled with a third input of the adder, the frequency control word accumulator being operative in the second mode of operation and non-operative in the first mode of operation.

3. The device of claim 2 , wherein an output of the modulo operator is coupled with a first input of a multiplexer, an output of the multiplexer being coupled with the first input of the adder, the multiplexer further having a second input, and wherein the multiplexer is adapted to select the first input in the first mode of operation and the second input in the second mode of operation.

4. The device of claim 1 , wherein the first input of the adder is a positive input of the adder and the second input of the adder is a negative input of the adder.

5. The device of claim 1 , further comprising a controllable oscillator coupled to an output of the adder, and a loop filter coupled between the output of the adder and the controllable oscillator.

6. The device of claim 5 , further comprising a cycle counter, a first input of the cycle counter being coupled to an output of the oscillator, a second output of the cycle counter being coupled to a data input, and an output of the cycle counter being coupled to the modulo operation, the cycle counter being adapted to count a number of cycles of an output signal of the oscillator between edges of a signal at a data input.

7. The device of claim 6 , further comprising a further multiplexer, a first input of the further multiplexer being coupled to the data input, a second input of the further multiplexer being coupled to a reference frequency input, and an output of the further multiplexer being coupled to the second input of the cycle counter.

8. The device of claim 6 , further comprising a phase sampler, the phase sampler being adapted to receive a plurality of output signals of the oscillator, an output of the phase sampler being coupled to the phase input of the phase detector.

9. The device of claim 1 , wherein the device is switchable between a phase locked loop (PLL) mode of operation and a clock recovery mode of operation.

10. The device of claim 1 , wherein the phase detector is part of a phase locked loop, wherein, for clock recovery, the device is adapted to:
in an initialization phase, lock the phase locked loop to a periodic data pattern, and
after the initialization phase, adapt the locking of the phase locked loop to random data.

11. A device, comprising:
an oscillator;
a counter, a first input of the counter being coupled to an output of the oscillator and a second input of the counter being coupled to a data input;
a modulo operator being coupled to an output of the counter;
a phase detector being coupled to an output of the modulo operator; and
a loop filter being coupled to an output of the phase detector, wherein an output of the loop filter is coupled with a control input of the oscillator.

12. The device of claim 11 , wherein a frequency of the oscillator is N times a frequency of a data clock underlying a data signal at the data input, and
wherein the modulo operator is a modulo N operator.

13. The device of claim 11 , wherein the device is an all digital device.

14. A method, comprising:
locking an oscillator on a reference pattern; and
performing clock recovery during a random data transfer after the locking, wherein performing the clock recovery comprises performing a modulo operation on a number of cycles of an oscillator output signal between edges of the random data.

15. The method of claim 14 , wherein performing the clock recovery further comprises controlling an oscillator based on an output of the modulo operation.

16. The method of claim 14 , wherein a frequency of the oscillator output signal is N times a frequency of the random data, wherein the modulo operation is a modulo N operation.

17. The method of claim 16 , wherein N is an even number.

18. The method of claim 16 , wherein N is at least 4.

19. The method of claim 14 , further comprising selecting a mode of operation, wherein the locking and the performing is performed in a first mode of operation, and wherein in a second mode of operation a locking on a reference frequency is performed.

20. The method of claim 19 , further comprising selecting the first mode of operation when the method is performed in a slave device, and selecting the second mode of operation when the method is performed in a master device.

Assignees

• Infineon Technologies Ag

Inventors

• Grollitsch Werner
• Nonis Roberto

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/1806

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H04L7/0054

  Detection of the synchronisation error by features other than the received signal transition (by means of signal transition H04L7/033) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title