Rescaling

Patent metadata

Field	Value
Publication number	US-9257986-B2
Application number	US-201414166667-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	Jun 23, 2010
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

First claim

What is claimed is:

1. An integrated circuit (“IC”) comprising:
N sets of configurable circuits for jointly processing a set of data signals at a first data rate, wherein each set of configurable circuits processes the set of data signals at a second data rate that is a fraction of the first data rate, wherein each set of the configurable circuits reconfigure at each reconfiguration clock cycle, and wherein the N sets of configurable circuits comprise respective rescaled portions…

Assignees

• Altera Corp

Inventors

• Weber Scott J
• Ebeling Christopher D
• Caldwell Andrew
• Teig Steven
• Callahan Timothy J
• Nguyen Hung Q
• Sun Shangzhi
• Yeole Shilpa V

Classifications

• G06F30/327

  Physics · mapped topic

• H03K19/17736 Primary

  Electricity · mapped topic

• G06F17/505

  Physics · mapped topic