Method for producing an optoelectronic semiconductor chip, and optoelectronic semiconductor chip

Patent metadata

Field	Value
Publication number	US-9257612-B2
Application number	US-201113704600-A
Country	US
Kind code	B2
Filing date	May 26, 2011
Priority date	Jun 17, 2010
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method for producing an optoelectronic semiconductor chip is specified, comprising the following steps: providing an n-conducting layer ( 2 ), arranging a p-conducting layer ( 4 ) on the n-conducting layer ( 2 ), arranging a metal layer sequence ( 5 ) on the p-conducting layer ( 4 ), arranging a mask ( 6 ) at that side of the metal layer sequence ( 5 ) which is remote from the p-conducting layer ( 4 ), in places removing the metal layer sequence ( 5 ) and uncovering the p-conducting layer ( 4 ) using the mask ( 6 ), and in places neutralizing or removing the uncovered regions ( 4 a ) of the p-conducting layer ( 4 ) as far as the n-conducting layer ( 2 ) using the mask ( 6 ), wherein the metal layer sequence ( 5 ) comprises at least one mirror layer ( 51 ) and a barrier layer ( 52 ), and the mirror layer ( 51 ) of the metal layer sequence ( 5 ) faces the p-conducting layer ( 4 ).

First claim

The invention claimed is:

1. A method for producing an optoelectronic semiconductor chip comprising the following method steps performed in the indicated order:
providing an n-conducting layer;
arranging a p-conducting layer on the n-conducting layer, wherein at least one active zone provided for receiving and/or for emitting electromagnetic radiation during the operation of the optoelectronic semiconductor chip is formed between the n-conducting layer and the p-conducting layer;
arranging a metal layer sequence on the p-conducting layer;
arranging a mask at a side of the metal layer sequence which is remote from the p-conducting layer;
in places removing the metal layer sequence and uncovering the p-conducting layer using the mask; and
in places neutralizing or removing the uncovered regions of the p-conducting layer as far as the n-conducting layer using the mask,
wherein the metal layer sequence comprises at least one mirror layer and a barrier layer, and the mirror layer of the metal layer sequence faces the p-conducting layer.

2. The method according to claim 1 , wherein an opening is formed which extends through the n conducting layer and the p-conducting layer, a layer of the metal layer sequence is uncovered at a bottom area of the opening, a connection pad for making electrical contact with the semiconductor chip is formed at the bottom area, the opening at least partly extends through the mirror layer of the metal layer sequence, a side area of the opening is completely covered by a passivation layer at least in the region of the mirror layer, and the passivation layer is produced by means of an ALD process.

3. The method according to claim 1 , wherein the n-conducting layer, the p-conducting layer and the active zone are based on a nitride semiconductor.

4. The method according to claim 1 , wherein an insulation layer is applied to a surface remote from a growth substrate, and wherein the insulation layer covers the uncovered regions of the n-conducting layer and all uncovered outer areas of the p-conducting layer, of the active zone and of the metal layer sequence.

5. The method according to claim 4 , wherein the insulation layer is opened by the production of openings towards the n-conducting layer.

6. The method according to claim 1 , wherein the n-conducting layer is not removed throughout its entire thickness even in those places where the p-conducting layer is removed.

7. A method for producing an optoelectronic semiconductor chip comprising:
providing an n-conducting layer;
arranging a p-conducting layer on the n-conducting layer;
arranging a metal layer sequence on the p-conducting layer, wherein the metal layer sequence comprises at least one mirror layer and a barrier layer and the mirror layer of the metal layer sequence faces the p-conducting layer;
arranging a mask at that side of the metal layer sequence which is remote from the p-conducting layer;
in places removing the metal layer sequence and uncovering the p-conducting layer using the mask;
in places neutralizing or removing the uncovered regions of the p-conducting layer as far as the n-conducting layer using the mask;
applying an insulation layer to cover the uncovered regions of the n-conducting layer and uncovered outer areas of the p-conducting layer, of the active zone and of the metal layer sequence;
forming a plurality of openings throughout the insulation layer towards the n-conducting layer; and
applying a metal layer onto the insulation layer so that the metal layer is electrically conductively connected to the n-conducting layer throughout the openings.

Assignees

• Höppel Lutz
• Von Malm Norwin
• Osram Opto Semiconductors Gmbh

Inventors

• Höppel Lutz
• Von Malm Norwin

Classifications

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/855

  Optical field-shaping means, e.g. lenses · CPC title

• H10H20/817

  characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous · CPC title

• H10H20/81

  Bodies · CPC title