Semiconductor devices including a stressor in a recess and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9257520-B2
Application number	US-201514680349-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Nov 22, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a lightly doped drain (LDD) in an active region in a substrate;
forming a fast etching region comprising phosphorous in the LDD;
forming a first trench in the active region by recessing the fast etching region;
forming a second trench in the active region by enlarging the first trench using a directional etch process, wherein the second trench comprises a notched portion of the active region;
forming an embedded stressor in the second trench; and
forming a gate electrode on the active region,
wherein the embedded stressor comprises a lower semiconductor layer and an upper semiconductor layer,
wherein the upper semiconductor layer comprises a first width narrower than a second width of the lower semiconductor layer, and alignment of a side surface of the upper semiconductor layer is offset from an outer side surface of the lower semiconductor layer, and
wherein an uppermost surface of the upper semiconductor layer is higher than an uppermost surface of the active region.

2. The method of claim 1 , further comprising:
forming a spacer between the upper semiconductor layer and the gate electrode, wherein the spacer contacts an uppermost surface of the lower semiconductor layer and a side of the upper semiconductor layer.

3. The method of claim 1 , wherein forming the lower semiconductor layer comprises:
forming a first semiconductor layer in the second trench; and
forming a second semiconductor layer on the first semiconductor layer,
wherein the second semiconductor layer comprises boron and germanium, and a germanium concentration of the second semiconductor layer is greater than a germanium concentration of the first semiconductor layer.

4. The method of claim 1 , wherein a portion of the fast etching region is between the LDD and the embedded stressor, after forming the embedded stressor.

5. The method of claim 2 , wherein forming the embedded stressor comprises:
forming the lower semiconductor layer in the second trench;
forming the spacer on the lower semiconductor layer; and
forming the upper semiconductor layer contacting a side of the spacer on the lower semiconductor layer.

6. The method of claim 5 , further comprising:
forming a recess in the lower semiconductor layer before forming the upper semiconductor layer, wherein forming the recess comprises etching the lower semiconductor layer using the spacer as an etch mask, and wherein at least a portion of the upper semiconductor layer is in the recess.

7. The method of claim 3 , wherein forming the first semiconductor layer, the second semiconductor layer, and the upper semiconductor layer comprises performing at least one selective epitaxial growth (SEG) process.

8. A method of forming a semiconductor device, the method comprising:
forming a first gate electrode on a first active region in a first region of a substrate and a second gate electrode on a second active region in a second region of the substrate, wherein the first and second regions comprise different respective pattern densities;
forming a first spacer on a side of the first gate electrode and a second spacer on a side of the second gate electrode;
forming a first additional spacer on the first spacer and a second additional spacer on the second spacer;
forming a first trench in the first active region adjacent the side of the first gate electrode and a second trench in the second active region adjacent the side of the second gate electrode; and
forming a first embedded stressor in the first trench and a second embedded stressor in the second trench,
wherein the first embedded stressor comprises a first lower semiconductor layer and a first upper semiconductor layer on the first lower semiconductor layer,
wherein a lowermost portion of the first upper semiconductor layer is lower than an uppermost surface of the first lower semiconductor layer,
wherein the second embedded stressor comprises a second lower semiconductor layer and a second upper semiconductor layer on the second lower semiconductor layer, and
wherein the first upper semiconductor layer comprises a first thickness greater than a second thickness of the second upper semiconductor layer.

9. The method of claim 8 , wherein a first vertical distance between the uppermost surface of the first lower semiconductor layer and an uppermost surface of the second lower semiconductor layer is greater than a second vertical distance between an uppermost surface of the first upper semiconductor layer and an uppermost surface of the second upper semiconductor layer.

Assignees

• Shin Dong-Suk
• Kang Hyun-Chul
• Roh Dong-Hyun
• Park Pan-Kwi
• Shin Geo-Myung
• Lee Nae-In
• Lee Chul-Woong
• Chung Hoi-Sung
• Kim Young-Tak
• Samsung Electronics Co Ltd

Inventors

• Shin Dong-Suk
• Kang Hyun-Chul
• Roh Dong-Hyun
• Park Pan-Kwi
• Shin Geo-Myung
• Lee Nae-In
• Lee Chul-Woong
• Chung Hoi-Sung
• Kim Young-Tak

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0133

  Manufacturing common source or drain regions between multiple IGFETs · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title