Semiconductor device including graded gate stack, related method and design structure

Patent metadata

Field	Value
Publication number	US-9257519-B2
Application number	US-201314081417-A
Country	US
Kind code	B2
Filing date	Nov 15, 2013
Priority date	Apr 23, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate; and
a gate structure disposed directly on the substrate, the gate structure including:
a graded region with a varied material concentration profile, wherein the graded region contains magnesium (Mg), the graded region including:
a first portion in direct contact with a top surface of the substrate and a second portion proximate to and directly under the metal layer, the first portion comprising substantially silicon and the second portion comprising substantially metal; and

a metal layer disposed on the graded region.

2. The semiconductor device of claim 1 , wherein the graded region further contains at least one of aluminum (Al), lanthanum (La), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), and zirconium oxide (Zr 2 O 3 ).

3. The semiconductor device of claim 1 , wherein a concentration of each material in the graded region varies linearly.

4. The semiconductor device of claim 1 , wherein a concentration of each material in the graded region varies exponentially.

5. The semiconductor device of claim 1 , wherein the graded region includes a plurality of films, the plurality of films having a varied material composition relative one another.

6. A design structure tangibly embodied in a machine readable medium for design, manufacturing, or testing a semiconductor device, the design structure comprising:
a substrate; and
a gate structure disposed directly on the substrate, the gate structure including:
a graded region with a varied material concentration profile, wherein the graded region contains magnesium (Mg), the graded region including:
a first portion in direct contact with a top surface of the substrate and a second portion proximate and directly under the metal layer, the first portion comprising substantially silicon and the second portion comprising substantially metal; and

a metal layer disposed on the graded region.

7. The design structure of claim 6 , wherein the graded region further contains at least one of aluminum (Al), lanthanum (La), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), and zirconium oxide (Zr 2 O 3 ).

8. The design structure of claim 6 , wherein the graded region includes a plurality of films, the plurality of films having a varied material composition relative one another.

Assignees

• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Chudzik Michael P
• Dai Min
• Liu Jinping
• Shepard Jr Joseph F
• Wong Keith K H

Classifications

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title