Connection structure for an integrated circuit with capacitive function

Patent metadata

Field	Value
Publication number	US-9257499-B2
Application number	US-201313914820-A
Country	US
Kind code	B2
Filing date	Jun 11, 2013
Priority date	Dec 20, 2010
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced.

First claim

The invention claimed is:

1. A terminal structure for an integrated circuit chip, comprising:
a connection pad within the integrated circuit chip and forming an electrode of a first capacitor, wherein at least a portion of an upper surface of the connection pad is exposed through an opening of the integrated circuit chip, said exposed portion of the upper surface configured for making an electrical connection outside of the integrated circuit chip; and
a first conductor disposed within the integrated circuit chip and forming another electrode of the first capacitor that is directly connected to a ground of the integrated circuit chip;
wherein the opening for the exposed portion of the connection pad and the first conductor are vertically aligned with each other in a direction perpendicular to said upper surface;
a mechanical reinforcement structure comprising a plurality of first stacks of at least two vias and two metal lines that are electrically connected to, and extend perpendicularly from, a bottom surface of the connection pad; and
a plurality of second stacks of at least two vias and two metal lines that are electrically connected to, and extend perpendicularly from, an upper surface of the first conductor;
wherein at least one of the second stacks is positioned in a gap between two of the first stacks and adjacent to the connection pad.

2. The terminal structure of claim 1 wherein the first conductor is parallel to the connection pad.

3. The terminal structure of claim 1 :
wherein each first stack forms a second conductor electrically coupled to the connection pad and extending through the integrated circuit chip from the connection pad toward the first conductor; and
wherein each second stack forms a third conductor electrically coupled to the first conductor, extending through the integrated circuit chip from the first conductor toward the connection pad, and laterally adjacent to the second conductor.

4. The terminal structure of claim 1 , wherein a metal line of the first stack is electrically coupled to the connection pad is disposed at a same level as a metal line of the second stack electrically coupled to the first conductor.

5. The terminal structure of claim 1 , further including a second conductor forming an electrode of a second capacitor that has another electrode formed by one of the connection pad and first conductor.

6. The terminal structure of claim 1 , further including a second conductor disposed at a same level as the first conductor and forming an electrode of a second capacitor that has another electrode formed by one of the connection pad and first conductor.

7. The terminal structure of claim 1 , further including:
a second conductor galvanically isolated from the connection pad and first conductor and forming an electrode of a second capacitor; and
a third conductor galvanically isolated from the connection pad and first conductor and forming another electrode of the second capacitor.

8. The terminal structure of claim 1 , wherein the connection pad comprises a further conductor and an outer metal layer coated on an upper surface of the further conductor within the opening formed in the integrated circuit chip.

9. An integrated circuit chip, comprising:
a plurality of metallization layers including:
an upper metallization layer having an upper surface exposed by an opening formed in said integrated circuit chip; and
another metallization layer below the upper metallization layer directly connected to a ground of the integrated circuit chip;

wherein the opening exposing the upper surface of the upper metallization layer and the another metallization layer are vertically aligned with each other in a direction perpendicular to said exposed upper surface; and
wherein the upper metallization layer and said another metallization layer form first and second plates of a capacitor; and
wherein said plurality of metallization layers further include at least one further metallization layer positioned between the upper and another metallization layers, said at least one further metallization layer configured to form:
a mechanical reinforcement structure comprising a plurality of first stacks, wherein each first stack comprises a metal line formed from the at least one further metallization layer with a via electrically connected to a bottom surface of the upper metallization layer; and
a plurality of second stacks, wherein each second stack comprises a metal line formed from the at least one further metallization layer with a via electrically connected to an upper surface of the another metallization layer;
wherein at least one of the second stacks is positioned in a gap between two of the first stacks.

Assignees

• St Microelectronics Srl

Inventors

• Pagani Alberto

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L28/60

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic