Method of making a split gate non-volatile memory (NVM) cell and a logic transistor

Patent metadata

Field	Value
Publication number	US-9257445-B2
Application number	US-201414291224-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate.

First claim

The invention claimed is:

1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) cell in an NVM region of the substrate, the method comprising:
forming a charge storage layer over the substrate;
depositing a first conductive layer over the charge storage layer;
depositing a capping layer over the first conductive layer;
patterning the capping layer, the first conductive layer, and the charge storage layer to form a control gate stack in the NVM region;
forming a high-k dielectric layer over the substrate including over the control gate stack;
forming a metal layer over the high-k dielectric layer;
depositing a second conductive layer over the metal layer;
patterning the second conductive layer and the metal layer to form a remaining portion of the second conductive layer and a remaining portion of the metal layer over a portion of the control gate stack and adjacent to a first side of the control gate stack;
removing the remaining portion of the second conductive layer to form a select gate stack, wherein the select gate stack comprises the remaining portion of the metal layer; and
depositing a stressor layer over the substrate including over the control gate stack and over the select gate stack.

2. The method of claim 1 , further comprising:
forming an insulating sidewall spacer on each side of the control gate stack prior to the forming the high-k dielectric layer.

3. The method of claim 1 , wherein the semiconductor structure further comprises a logic transistor in a logic region of the substrate, the method further comprising:
removing the capping layer, the first conductive layer, and the charge storage layer from the logic region prior to forming the high-k dielectric layer.

4. The method of claim 3 , further comprising:
patterning the second conductive layer, the metal layer, and the high-k dielectric layer to form a logic gate stack in the logic region.

5. The method of claim 4 , further comprising:
forming a first set of sidewall spacers on sides of the logic gate stack prior to the depositing the stressor layer; and
forming a second set of sidewall spacers on sides of the split gate NVM cell prior to the depositing the stressor layer.

6. The method of claim 5 , further comprising:
removing the second set of sidewall spacers from each side of the split gate NVM cell prior to the depositing the stressor layer.

7. The method of claim 1 , further comprising:
the patterning the second conductive layer and the metal layer further comprises
patterning the high-k dielectric layer to leave a remaining portion of the high-k dielectric layer over the portion of the control gate stack and adjacent to the first side of the control gate stack, wherein
the removing the remaining portion of the second conductive layer further leaves the remaining portion of the high-k dielectric layer between the control gate stack and the remaining portion of the metal layer, and
the select gate stack further comprises the remaining portion of the high-k dielectric layer.

8. The method of claim 1 , wherein
the stressor layer has tensile stress,
the stressor layer induces lateral compressive stress in a channel direction in a first region of the substrate under the select gate stack and in a second region of the substrate adjacent to a second side of the control gate stack,
the second side of the control gate stack is on an opposite side of the split gate NVM cell from the select gate stack,
a third region of the substrate is located under the control gate stack between the first region and the second region, and
lateral tensile stress is induced in the third region of the substrate.

9. The method of claim 1 , wherein
the stressor layer has tensile stress, and
lateral stress in a first region in the substrate under the select gate stack is less tensile than lateral stress in a second region in the substrate under the control gate stack.

10. A semiconductor structure using a substrate having a non-volatile memory (NVM) region, comprising:
a split gate NVM cell comprising:
a control gate stack comprising a charge storage layer over the substrate, a first conductive layer over the charge storage layer, and a capping layer over the first conductive layer, and
a select gate stack laterally adjacent to a first side of the control gate stack, the select gate stack comprising a high-k dielectric layer over the substrate, along the first side of the control gate stack, and over a top surface of the control gate stack, and a metal layer over the high-k dielectric layer; and

a stressor layer over the split gate NVM cell.

11. The semiconductor structure of claim 10 , the substrate further having a logic region, wherein the semiconductor structure further comprises:
a logic gate stack in the logic region, the logic gate stack comprising the high-k dielectric layer over the substrate, the metal layer over the high-k dielectric layer, and a second conductive layer over the metal layer.

12. The semiconductor structure of claim 11 , wherein the semiconductor structure further comprises:
an insulating sidewall spacer on each side of the logic gate stack.

13. The semiconductor structure of claim 11 , wherein the semiconductor structure further comprises:
the stressor layer over the logic gate stack.

14. The semiconductor structure of claim 10 , wherein the semiconductor structure further comprises:
an insulating sidewall spacer on each side of the control gate stack.

15. The semiconductor structure of claim 10 , wherein the semiconductor structure further comprises:
source/drain implant regions in the substrate adjacent to a second side of the control gate stack and adjacent to a first side of the select gate stack, wherein the second side of the control gate stack is on an opposite side of the split gate NVM cell from the first side of the select gate stack.

16. The semiconductor structure of claim 11 , wherein the semiconductor structure further comprises:
source/drain implant regions in the substrate adjacent to a first side of the logic gate stack and adjacent to a second side of the logic gate stack, wherein the first side of the logic gate stack is opposite from the second side of the logic gate stack.

17. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) structure in an NVM region of the substrate, the method comprising:
forming a charge storage layer over the substrate;
depositing a first polysilicon layer over the charge storage layer;
depositing a capping layer over the first polysilicon layer;
patterning the capping layer, the first polysilicon layer, and the charge storage layer to leave a control gate stack in the NVM region, wherein the control gate stack comprises remaining portions of the capping layer, the first polysilicon layer, and the capping layer;
forming a high-k dielectric layer over the substrate including over the control gate stack;
forming a metal layer over the high-k dielectric layer;
depositing a second polysilicon layer over the metal layer;
patterning the second polysilicon layer and the metal layer to leave a remaining portion of the metal layer over the substrate, along a first side of the control gate stack, and over a top surface of the remaining portion of the capping layer, and to leave a remaining portion of the second polysilicon layer over the remaining portion of the metal layer;
removing the remaining po

Assignees

• Loiko Konstantin V
• Winstead Brian A
• Freescale Semiconductor Inc

Inventors

• Loiko Konstantin V
• Winstead Brian A

Classifications

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title