Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Patent metadata

Field	Value
Publication number	US-9257410-B2
Application number	US-201113012644-A
Country	US
Kind code	B2
Filing date	Jan 24, 2011
Priority date	Feb 3, 2010
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a semiconductor substrate having
a first surface,
a second surface that is disposed opposite to the first surface, wherein (i) at least a first portion of the first surface is recessed relative to a second portion of the first surface to form a first recessed region of the semiconductor substrate and (ii) a second recessed region is formed from at least a portion of the second surface of the semiconductor substrate, and
one or more vias formed in the first recessed region of the semiconductor substrate, the one or more vias to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate;

a first die coupled to the semiconductor substrate, the first die being electrically coupled to the one or more vias formed in the first recessed region of the semiconductor substrate;
a first redistribution layer formed on the first surface of the semiconductor substrate, wherein (i) the first die is coupled to the first surface of the semiconductor substrate via the first redistribution layer, and (ii) the first die is coupled to the first redistribution layer via one or more first bumps;
a second redistribution layer formed on the second surface of the semiconductor substrate; and
a second die (i) coupled to the second surface of the semiconductor substrate via the second redistribution layer, and (ii) coupled to the second redistribution layer via one or more second bumps.

2. The apparatus of claim 1 , wherein the first recessed region of the semiconductor substrate has a first thickness that is smaller than a second thickness of a region of the semiconductor substrate that is external to the first recessed region.

3. The apparatus of claim 2 , wherein the second die is coupled to the region of the semiconductor substrate having the second thickness.

4. The apparatus of claim 2 , wherein the first die is disposed on the region of the semiconductor substrate having the second thickness.

5. The apparatus of claim 2 , wherein the one or more vias comprise one or more first vias, and wherein the apparatus further comprises:
one or more second vias formed in the region of the semiconductor substrate having the second thickness, wherein the one or more second vias are disposed on only one of (i) the first surface or (ii) the second surface of the semiconductor substrate.

6. The apparatus of claim 1 , wherein the first redistribution layer is electrically coupled to the one or more vias to route electrical signals of the first die.

7. The apparatus of claim 6 , further comprising:
one or more package interconnect structures (i) coupled to the first surface of the semiconductor substrate and (ii) electrically coupled to the first redistribution layer, the one or more package interconnect structures to further route the electrical signals of the first die.

8. The apparatus of claim 7 , wherein the one or more package interconnect structures comprise at least one of solder balls or metal posts.

9. The apparatus of claim 7 , further comprising:
a printed circuit board coupled to the semiconductor substrate using the one or more package interconnect structures.

10. The apparatus of claim 7 , wherein:
the one or more package interconnect structures are a first set of package interconnect structures; and
the apparatus further comprises:
a second set of package interconnect structures (i) coupled to the second surface of the semiconductor substrate and (ii) electrically coupled to the second redistribution layer, the second set of package interconnect structures to further route the electrical signals of at least one of the first die or the second die.

11. The apparatus of claim 1 , wherein the second die is coupled to (i) the first recessed region and (ii) the second surface of the semiconductor substrate in a flip-chip configuration, the second die being electrically coupled to the one or more vias.

12. The apparatus of claim 1 , wherein the first die is coupled to the first surface of the semiconductor substrate in a flip-chip configuration.

13. The apparatus of claim 1 , wherein the first die is coupled to the first recessed region.

14. The apparatus of claim 1 , wherein:
the semiconductor substrate comprises silicon;
the first die, the second die, or both comprise silicon; and
the one or more vias comprise through-silicon vias (TSVs).

15. The apparatus of claim 1 , wherein the semiconductor substrate is recessed such that the first recessed region has a thickness between 10 microns and 500 microns.

16. The apparatus of claim 1 , wherein:
an active side of the second die is coupled opposite to an active side of the first die; and
the active side of the first die is coupled to the first redistribution layer via the one or more first bumps on the first redistribution layer, and the active side of the second die is coupled to the second redistribution layer via the one or more second bumps on the second redistribution layer.

17. The apparatus of claim 1 , wherein the second die is disposed in the second recessed region.

18. The apparatus of claim 17 , wherein:
the one or more vias are one or more first vias; and
the second recessed region includes one or more second vias formed in the second recessed region, the one or more second vias to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate.

19. The apparatus of claim 1 , further comprising:
a molding compound disposed on at least one of (i) the first surface or (ii) the second surface of the semiconductor substrate, the molding compound being further disposed to substantially encapsulate at least one of the first die or the second die.

20. An apparatus comprising:
a semiconductor substrate having
a first surface,
a second surface that is disposed opposite to the first surface, wherein a first portion of the first surface is recessed to form a first recessed region of the semiconductor substrate and a second portion of the second surface is recessed to form a second recessed region of the semiconductor substrate, and
one or more vias formed in the first recessed region of the semiconductor substrate, the one or more vias to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate;

a die coupled to the semiconductor substrate, wherein
the die is coupled to the first surface of the semiconductor substrate,
the die is coupled to the first recessed region,
the die is electrically coupled to the one or more vias formed in the first recessed region of the semiconductor substrate, and
the die is coupled to the semiconductor substrate in a flip-chip configuration;

a molding compound disposed (i) in direct contact with at least a portion of a surface of the die and (ii) on at least one of the first surface or the second surface of the semiconductor substrate;
a first redistribution layer (i) formed on the second surface of the semiconductor substrate and (ii) electrically coupled to the one or more vias to route electrical signals of the die;
one or more first package interconnect structures (i) coupled to the second surface of the semiconductor substrate and (ii) electrically coupled to the first redistribution layer to further route the electrical signals of the die;
a second redistribution layer (i) formed on the first surface of the semiconductor substrate and (ii) electrically coupled to the one or more vias

Assignees

• Wu Albert
• Chen Roawen
• Han Chung Chyung
• Liou Shiann-Ming
• Wei Chien-Chuan
• Chang Runzi
• Wu Scott
• Cheng Chuan-Cheng
• Marvell World Trade Ltd

Inventors

• Wu Albert
• Chen Roawen
• Han Chung Chyung
• Liou Shiann-Ming
• Wei Chien-Chuan
• Chang Runzi
• Wu Scott
• Cheng Chuan-Cheng

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title