Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9257408-B2
Application number	US-201214435932-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A soldering portion ( 4 ) and a Ni plating mark ( 5 ) are simultaneously forming by plating on a wiring pattern ( 2 ) of an insulating substrate ( 1 ). A semiconductor chip ( 6 ) is mounted on the insulating substrate ( 1 ). A position of the insulating substrate ( 1 ) is recognized by the Ni plating mark ( 5 ) and a wire ( 7 ) is bonded to the semiconductor chip ( 6 ). An electrode ( 8 ) is joined to the soldering portion ( 4 ) by solder ( 9 ). The insulating substrate ( 1 ), the semiconductor chip ( 6 ), the wire ( 7 ), and the electrode ( 8 ) are encapsulated in an encapsulation material ( 13 ).

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor device comprising:
simultaneously forming a soldering portion and a mark by plating on a wiring pattern of an insulating substrate;
mounting a semiconductor chip on the insulating substrate;
recognizing a position of the insulating substrate by the mark and bonding a wire to the semiconductor chip;
joining an electrode to the soldering portion by a solder; and
encapsulating the insulating substrate, the semiconductor chip, the wire, and the electrode in an encapsulation material.

2. A method of manufacturing a semiconductor device comprising:
forming a soldering portion and a mark on a wiring pattern of an insulating substrate;
mounting a semiconductor chip on the insulating substrate;
recognizing a position of the insulating substrate by the mark and bonding a wire to the semiconductor chip;
joining an electrode to the soldering portion by a solder; and
encapsulating the insulating substrate, the semiconductor chip, the wire, and the electrode in an encapsulation material,
wherein a spacing between the soldering portion and the mark is set to at least 5 mm.

3. A semiconductor device comprising:
an insulating substrate including a wiring pattern;
a soldering portion provided on the wiring pattern;
a mark provided on the wiring pattern and formed of same material as the soldering portion;
a semiconductor chip mounted on the insulating substrate;
a wire bonded to the semiconductor chip;
an electrode joined to the soldering portion by a solder; and
an encapsulation material encapsulating the insulating substrate, the semiconductor chip, the wire, and the electrode.

Assignees

• Matsumoto Takayuki
• Onishi Hirotaka
• Koga Masuo
• Mitsubishi Electric Corp

Inventors

• Matsumoto Takayuki
• Onishi Hirotaka
• Koga Masuo

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/07536

  Soldering or alloying · CPC title