Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitance

Patent metadata

Field	Value
Publication number	US-9257322-B2
Application number	US-201213598586-A
Country	US
Kind code	B2
Filing date	Aug 29, 2012
Priority date	Jul 4, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.

First claim

What is claimed is:

1. A method for manufacturing a through substrate via (TSV), comprising:
providing a substrate having a first surface and a second surface;
forming a trench in the first surface of the substrate;
filling a low resistance material into the trench;
forming an insulating layer on the first surface of the substrate;
forming at least one opening in the first surface of the substrate, wherein a location of the at least one opening is different from a location of the trench;
forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the at least one opening and on the insulating layer above the first surface;
filling a conductive material into the at least one opening, wherein the at least one opening is used to form at least one via; and
after filling the conductive material into the at least one opening, forming a body contact hole on the first surface of the substrate, wherein a location of the body contact hole is the same as the location of the trench.

2. The method for manufacturing the TSV according to claim 1 , wherein the trench is located at a geometric center with respect to the at least one opening.

3. The method for manufacturing the TSV according to claim 1 , after forming the body contact hole on the first surface of the substrate, further comprising:
filling the low resistance material or the conductive material into the body contact hole.

4. The method for manufacturing the TSV according to claim 1 , wherein the insulating layer is formed by a first silicon nitride layer, a first silicon oxide layer and a second silicon nitride layer.

5. The method for manufacturing the TSV according to claim 1 , wherein method of filling the low resistance material into the trench comprises:
forming a low resistance epi-layer on the first surface of the substrate, wherein the low resistance material of the low resistance epi-layer is filled into the trench; and
removing the low resistance epi-layer from the first surface.

6. The method for manufacturing the TSV according to claim 1 , wherein the low resistance material comprises p-type silicon, n-type silicon, or a conductive metal.

7. The method for manufacturing the TSV according to claim 1 , wherein the conductive material is copper.

8. The method for manufacturing the TSV according to claim 1 , wherein the method for filling the conductive material into the at least one opening comprises an electrochemical plating process or a chemical mechanical polishing process.

9. The method for manufacturing the TSV according to claim 1 , wherein a diameter of the trench or a diameter of the at least one opening is in the range of 0.1 nm to 3 mm.

10. The method for manufacturing the TSV according to claim 1 , wherein a diameter of the trench or a diameter of the at least one opening is in the range of 1 μm to 30 μm.

11. The method for manufacturing the TSV according to claim 1 , wherein a ratio of a depth of the trench to a depth of the at least one opening is in the range or 0.1% to 99.9%.

12. The method for manufacturing the TSV according to claim 1 , wherein a ratio of a depth of the trench to a depth of the at least one opening is in the range of 70% to 99.9%.

13. A control method of a TSV capacitance, comprising:
providing a substrate and the TSV capacitance, wherein the substrate includes a first surface and a second surface, wherein at least one opening is formed in the first surface of the substrate, wherein a conductive material, a conductive seed layer, a barrier layer and an oxide liner layer are disposed from interior to exterior on a sidewall of the at least one opening, and the TSV capacitance is formed between the conductive material and the substrate, wherein the at least one opening is used to form at least one via;
applying a first voltage to the conductive material of the at least one opening; and
applying a second voltage to the substrate to control the TSV capacitance.

14. The control method of the TSV capacitance according to claim 13 , further comprising:
forming a trench in the first surface of the substrate, wherein a location of the at least one opening is different from a location of the trench;
filling a low resistance material into the trench; and
applying the second voltage to the substrate through the trench.

15. The control method of the TSV capacitance according to claim 14 , wherein the location of the trench is at a geometric center with respect to the at least one opening.

16. The control method of the TSV capacitance according to claim 14 , further comprising:
forming a body contact hole on the first surface of the substrate and filling the low resistance material or the conductive material being into the body contact hole, wherein a location of the body contact hole is the same as the location of the trench; and
applying the second voltage to the substrate through the body contact hole and the trench.

Assignees

• Chen Erh-Hao
• Lin Cha-Hsin
• Ku Tzu-Kun
• Ind Tech Res Inst

Inventors

• Chen Erh-Hao
• Lin Cha-Hsin
• Ku Tzu-Kun

Classifications

• H10P14/60

  of insulating materials · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title