Memory devices and their operation having trim registers associated with access operation commands

Patent metadata

Field	Value
Publication number	US-9257182-B2
Application number	US-201213723781-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Dec 21, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Methods, and apparatus configured to perform methods, including loading trim settings into a trim register of a memory device associated with a command for an access operation, receiving the command for the access operation at the memory device, setting trims for the access operation in response to the trim settings of the trim register associated with the command for the access operation, and performing the access operation using the trims for the access operation; and including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims.

First claim

What is claimed is:

1. A method, comprising:
loading trim settings into a trim register of a memory device associated with a command for an access operation on an array of memory cells of the memory device;
receiving the command for the access operation at the memory device;
setting trims for the access operation in response to the trim settings of the trim register associated with the command for the access operation; and
performing the access operation using the trims for the access operations;
wherein loading the trim settings into the trim register occurs while performing a prior access operation on the array of memory cells.

2. The method of claim 1 further comprising:
loading trim settings into a trim register of the memory device associated with a command for a subsequent access operation on the array of memory cells;
receiving the command for the subsequent access operation at the memory device;
setting trims for the subsequent access operation in response to the trim settings of the trim register associated with the command for the subsequent access operation; and
performing the subsequent access operation using the trims for the subsequent access operation.

3. The method of claim 2 , wherein loading trim settings into the trim register associated with the command for the access operation comprises loading the trim settings into the trim register associated with the command for the access operation in response to another command received by the memory device.

4. The method of claim 2 , wherein loading trim settings into the trim register associated with the command for the subsequent access operation comprises loading the trim settings into the trim register associated with the command for the subsequent access operation in response to another command received by the memory device immediately preceding receiving the command for the subsequent access operation.

5. The method of claim 4 , further comprising receiving the another command while performing the access operation.

6. The method of claim 5 , further comprising receiving the command for the subsequent access operation at the memory device while performing the access operation.

7. The method of claim 2 , wherein loading trim settings into the trim register associated with the command for the access operation and loading trim settings into the trim register associated with the command for the subsequent access operation are performed in response to a single command received by the memory device.

8. The method of claim 1 , wherein loading the trim settings into the trim register occurs prior to receiving the command for the access operation.

9. The method of claim 1 , wherein loading trim settings into a trim register of a memory device associated with a command for an access operation on an array of memory cells of the memory device comprises loading trim settings into a first trim register of the memory device in response to a command for a first access operation on the array of memory cells, and loading trim settings into a second trim register of the memory device in response to a command for a subsequent access operation on the array of memory cells.

10. The method of claim 9 , further comprising toggling between the first trim register and the second trim register for loading trim settings in response to one or more next subsequent access commands.

11. The method of claim 9 , further comprising loading trim settings into a third trim register of the memory device in response to a command for a next subsequent access operation on the array of memory cells.

12. The method of claim 1 , wherein loading trim settings into a trim register of a memory device associated with a command for an access operation on the array of memory cells of the memory device comprises loading trim settings into an array of N trim registers of the memory device in response to receiving N commands for access operations on the array of memory cells, wherein N is an integer value, wherein each of the N trim registers are associated with a corresponding one of the N commands for access operations on the array of memory cells cycling from a first trim register of the array of N trim registers for a first command of the N commands for access operation on the array of memory cells to an Nth register of the array of N trim registers for an Nth command of the N commands for access operations on the array of memory cells.

13. The method of claim 12 , further comprising loading trim settings into the first trim register of the array of N trim registers in response to receiving a subsequent (N+1)th command for an access operation on the array of memory cells.

14. A method, comprising:
loading trim settings into a trim register of a memory device associated with a command for an access operation;
receiving the command for the access operation at the memory device;
setting trims for the access operation in response to the trim settings of the trim register associated with the command for the access operation; and
performing the access operation using the trims for the access operation;
wherein loading the trim settings into the trim register occurs after an indication that a cache register of the memory device is able to accept data input.

15. A method, comprising:
loading trim settings into a first trim register of a memory device in response to a command for a first access operation on the array of memory cells;
receiving the command for the first access operation at the memory device;
setting trims for the first access operation in response to the trim settings of the first trim register;
performing the first access operation using the trims for the first access operation;
loading trim settings into a second trim register of the memory device in response to a command for a subsequent access operation; and
further comprising transferring the trim settings from the second trim register to the first trim register prior to performing the subsequent access operation.

16. A method, comprising:
loading trim settings into a trim register of a memory device associated with a command for an access operation;
receiving the command for the access operation at the memory device;
setting trims for the access operation in response to the trim settings of the trim register associated with the command for the access operation; and
performing the access operation using the trims for the access operation;
wherein loading trim settings into the trim register associated with the command for the access operation and loading trim settings into the trim register associated with the command for the subsequent access operation are performed in response to a single command received by the memory device; and
wherein the single command received by the memory device comprises a command code and a confirm code, and further comprising receiving data at the memory device between receiving the command code and receiving the confirm code corresponding to the trim settings for both trim registers.

17. The method of claim 16 , further comprising receiving data at the memory device between receiving the command code and receiving the confirm code corresponding to the trim settings for at least one additional trim register.

18. A method, comprising:
loading trim settings into a trim register of a memory device associated with a command for an access operation;
receiving the command for the access operation at the memory device;
setting trims for the access operation in response to the trim settings of the trim register associated wit

Assignees

• Micron Technology Inc

Inventors

• Grunzke Terry

Classifications

• G06F2212/7207

  management of metadata or control data · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title