Address translation/specification field for hardware accelerator

Patent metadata

Field	Value
Publication number	US-9256729-B2
Application number	US-201313922304-A
Country	US
Kind code	B2
Filing date	Jun 20, 2013
Priority date	Jun 20, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

First claim

What is claimed is:

1. A computing system for an address translation/specification (ATS) field for a hardware accelerator, comprising:
the hardware accelerator communicatively coupled to a processor that is configured to execute user-space software, the hardware accelerator comprising a hardware module that is distinct from the processor, wherein the hardware accelerator is configured to perform a method comprising:
receiving a work queue entry from a work queue in a main memory by the hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software that is currently being executed by the processor that is communicatively coupled to the hardware accelerator, the work queue entry comprising a real memory address in the main memory for use in execution of the operation by the hardware accelerator, and a first ATS field that describes the real memory address in the work queue entry;
before executing the operation corresponding to the work queue entry by the hardware accelerator, determining, by the hardware accelerator, whether the first ATS field is consistent with the operation of the hardware accelerator corresponding to the work queue entry and the real memory address in the work queue entry;
based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the real memory address in the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator; and
based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the real memory address in the work queue entry, rejecting the work queue entry by the hardware accelerator.

2. The system of claim 1 , further comprising executing, by the processor that is communicatively coupled to the hardware accelerator, a generic driver to perform a method comprising:
receiving a control block corresponding to the operation of the hardware accelerator that is requested by the user-space software that is currently being executed by the processor from an application-specific library executing on the processor, the control block comprising a second ATS field and one or more virtual addresses;
performing a memory allocation corresponding to the one or more memory areas in the main memory based on the one or more virtual addresses and the second ATS field;
generating the work queue entry corresponding to the operation based on the memory allocation, the work queue entry comprising the real memory address corresponding to the one or more memory areas and the first ATS field;
pinning the one or more memory areas in the main memory; and
storing the generated work queue entry in the work queue in the main memory.

3. The system of claim 2 , wherein executing the operation corresponding to the work queue entry by the hardware accelerator comprises accessing the one or more memory areas in the main memory by the hardware accelerator.

4. The system of claim 2 , wherein the first ATS field in the work queue entry and the second ATS field in the control block are different.

5. The system of claim 1 , wherein the hardware accelerator comprises a field programmable gate array (FPGA) logic.

6. The system of claim 1 , the work queue entry comprising an invariant data portion, the invariant data portion comprising a plurality of fields; and
the first ATS field comprising a plurality of ATS subfields, and wherein each of the ATS subfields describes a respective field in the invariant data portion of the work queue entry.

7. The system of claim 1 , wherein the first ATS field comprises
a field indicating that a portion of the work queue entry comprises a scatter gather list of memory addresses.

8. The system of claim 1 , wherein the hardware accelerator comprises a networking processor.

9. The system of claim 1 , wherein the hardware accelerator comprises a graphics engine.

10. The system of claim 1 , wherein the first ATS field comprises a field indicating that a portion of the work queue entry comprises a flat memory address.

11. The system of claim 1 , wherein the first ATS field comprises a field indicating that a portion of the work queue entry comprises raw data.

12. The system of claim 1 , wherein the first ATS field comprises a field indicating a memory access mode comprising one of read only and read/write for the operation of the hardware accelerator.

13. The system of claim 1 , wherein the first ATS field comprises a field indicating that a portion of the work queue entry comprises a pointer to a child work queue entry in the work queue, the child work queue entry comprising a third ATS field and at least one of data and addressees corresponding to the operation of the hardware accelerator, and wherein executing the operation corresponding to the work queue entry by the hardware accelerator comprises processing the work queue entry and the child work queue entry.

14. The system of claim 4 , wherein the generic driver is further configured to:
determine a memory reference in the control block, wherein the second ATS field corresponds to the memory reference;
determining whether the memory reference is suitable for an operating system (OS) that is being executed by the processor;
based on determining that the memory reference in the control block is not suitable for the OS, substituting the memory reference in the control block with an equivalent representation of the memory reference that is suitable for the OS;
performing the memory allocation based on the equivalent representation of the memory reference; and
generating the work queue entry to include the equivalent representation of the memory reference as the real memory address in the work queue entry, and the first ATS field, wherein the first ATS field corresponds to the equivalent representation of the memory reference.

15. The system of claim 14 , wherein the memory reference comprises a flat address reference, and wherein the equivalent representation of the memory reference comprises a scatter gather list.

Assignees

• IBM

Inventors

• Haverkamp Frank
• Jacobi Christian
• Rider Scot H
• Sethi Vikramjit
• Swanberg Randal C
• Vogt Joerg-Stephan

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F9/545 Primary

  where tasks reside in different layers, e.g. user- and kernel-space · CPC title

• G06F21/74

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

• G06F21/51 Primary

  at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title