RAM memory device capable of simultaneously accepting multiple accesses

Patent metadata

Field	Value
Publication number	US-9256556-B2
Application number	US-201213653141-A
Country	US
Kind code	B2
Filing date	Oct 16, 2012
Priority date	Oct 21, 2011
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A RAM memory device includes a selection unit that supplies the access reaching one of two interfaces to a RAM in one cycle of a clock signal in response to a control signal. The RAM memory device also includes a storage unit that stores another access that has reached the other of the two interfaces at least till the next cycle following the above-mentioned one cycle in response to the control signal. The selection unit supplies the above-mentioned another access from the storage unit to the RAM in or after the above-mentioned next cycle.

First claim

What is claimed is:

1. A RAM memory device comprising:
a RAM that writes or reads data in synchronization with a clock signal in response to either a first access or a second access;
a flash side interface adapted to relay the first access including a first control signal and being supplied from a flash interface;
a processor side interface adapted to relay the second access including a second control signal and being supplied from a processor;
a RAM control signal storage that stores the second access having been relayed by the processor side interface in response to the first control signal; and
a multiplexer adapted to supply the first access having been relayed by the flash side interface to the RAM within one cycle of the clock signal in response to the first control signal, and to supply the second access which is stored in the RAM control signal storage to the RAM in or after a next cycle succeeding to said one cycle.

2. The RAM memory device of claim 1 , wherein each of the first and second control signals includes a selection instruction signal and a standby instruction signal,
the multiplexer supplies the first access or the second access in response to the selection instruction signal, and
the RAM control signal storage stores the second access in response to the standby instruction signal included in the first control signal having been relayed by the flash side interface.

3. The RAM memory device of claim 1 , wherein the RAM is a single-port RAM.

4. The RAM memory device of claim 1 , wherein the first and/or second data includes a page address of a flash memory and error information of data retrieved from the flash memory.

5. The RAM memory device of claim 1 , wherein the RAM memory device is included in a memory control device that controls a semiconductor memory device, and each of the first and second accesses is supplied from the memory control device in relation to control of the semiconductor memory device.

6. The RAM memory device of claim 4 , wherein the first data of the first access includes the error information, and the second data of the second access includes error-free data provided from outside.

7. The RAM memory device of claim 1 , wherein the RAM is a dual-port RAM.

8. The RAM memory device of claim 1 , wherein the selection unit includes a multiplexer.

9. A memory control device connected between a host device and a memory unit for writing and reading desired data into and from the memory unit in response to a command from the host device, said memory control device comprising:
a host interface that interfaces to the host device;
a memory interface that interfaces to the memory unit; and
a RAM device connected between the host interface and the memory interface,
said RAM device including:
a RAM that writes or reads data in synchronization with a clock signal in response to either a first access or a second access;
a flash side interface adapted to relay the first access including a first control signal and being supplied from a flash interface;
a processor side interface adapted to relay the second access including a second control signal and being supplied from a processor;
a RAM control signal storage that stores that second access having been relayed by the processor side interface in response to the first control signal; and
a multiplexer adapted to supply the first access having been relayed by the flash side interface to the RAM within one cycle of the clock signal in response to the first control signal, and to supply the second access which is stored in the RAM control signal storage to the RAM in or after a next cycle succeeding to said one cycle.

10. The memory control device of claim 9 , wherein the memory unit is a flash memory.

11. The memory control device of claim 9 , wherein the memory unit is a semiconductor memory device.

12. The memory control device of claim 9 further comprising an error check and correction (ECC) device for detecting and correcting error information in data supplied from the memory unit, before sending the data to the host device.

13. The memory control device of claim 9 further comprising an error check and correction (ECC) device for allotting a parity bit to data, if the desired data is to be written into the memory unit.

14. The memory control device of claim 9 , wherein the RAM is a single-port RAM.

15. The memory control device of claim 9 , wherein the RAM is a dual-port RAM.

16. The memory control device of claim 9 , wherein the first and/or second data includes a page address of a flash memory and error information of data retrieved from the flash memory.

17. The memory control device of claim 9 , wherein the selection unit includes a multiplexer.

Assignees

• Maeda Tomoyuki
• Lapis Semiconductor Co Ltd

Inventors

• Maeda Tomoyuki

Classifications

• G06F12/0623

  for memory modules · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/1642 Primary

  with request queuing · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title