Malware mitigation based on runtime memory allocation
US-2024220609-A1 · Jul 4, 2024 · US
Selective access to executable memory
US9256552B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9256552-B2 |
| Application number | US-201213683455-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 21, 2012 |
| Priority date | Nov 21, 2011 |
| Publication date | Feb 9, 2016 |
| Grant date | Feb 9, 2016 |
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Abstract
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In an embodiment, a data processing method comprises, in a computer executing a supervisor program: the supervisor program establishing a plurality of different memory access permissions comprising any combination of read, write, and execute permissions for one or more different regions of memory of a first domain; setting the memory access permissions of a first set of the regions of memory to execute only; in response to a request from a process to read or write a particular region of memory in the first set, performing one or more responsive actions that prevent the process from reading or modifying one or more instructions or one or more embedded immediate values of the particular region of memory. Embodiments provide selective access to executable memory.
First claim
Opening claim text (preview).
What is claimed is: 1. A computer-implemented method comprising: in a computer executing a supervisor program: the supervisor program establishing a plurality of different memory access permissions comprising any combination of read, write, and execute permissions for one or more different regions of memory of a first domain; setting the memory access permissions of a first set of the regions of memory to execute only; and in response to a request from a process to read or w…
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- G06F12/1416Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9256552B2 cover?
- In an embodiment, a data processing method comprises, in a computer executing a supervisor program: the supervisor program establishing a plurality of different memory access permissions comprising any combination of read, write, and execute permissions for one or more different regions of memory of a first domain; setting the memory access permissions of a first set of the regions of memory to…
- Who is the assignee on this patent?
- Cisco Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/1416. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).