Method and apparatus for content addressable memory parallel lookup
US-9159420-B1 · Oct 13, 2015 · US
US9256548B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9256548-B2 |
| Application number | US-201213688520-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 29, 2012 |
| Priority date | Nov 29, 2012 |
| Publication date | Feb 9, 2016 |
| Grant date | Feb 9, 2016 |
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In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
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What is claimed is: 1. A method, comprising: matching a virtual address simultaneously in parallel against a set of a plurality of predetermined rules in identifying one or more storing description parameters for converting the virtual address to a lookup address, with each of the plurality of predetermined rules including a range of one or more virtual addresses stored in a binary or ternary content-addressable memory entries, with said matching operation including performing a s…
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