Way preparation for accessing a cache

Patent metadata

Field	Value
Publication number	US-9256544-B2
Application number	US-201213726825-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Dec 26, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.

First claim

What is claimed is:

1. A method of accessing a cache comprising a plurality of ways, the method comprising:
storing access information for a first memory access indicating a subset of the plurality of ways, one of the subset accessed by the first memory access;
in response to a second memory access to the plurality of ways, the second memory access received after the first memory access:
initiating precharging all access lines for the plurality of ways;
determining the subse…

Assignees

• Crum Matthew M
• Tan Teik-Chung
• Advanced Micro Devices Inc

Inventors

• Crum Matthew M
• Tan Teik-Chung

Classifications

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F12/0895 Primary

  Physics · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F1/3275

  Physics · mapped topic

• Y02D10/00

  Cross-Sectional Technologies · mapped topic