Memory system and host device
US-2024394189-A1 · Nov 28, 2024 · US
US9256540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9256540-B2 |
| Application number | US-21293508-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 18, 2008 |
| Priority date | Sep 18, 2008 |
| Publication date | Feb 9, 2016 |
| Grant date | Feb 9, 2016 |
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A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.
Opening claim text (preview).
What is claimed is: 1. A method of performing cache injection in a processor system, comprising: monitoring, at a cache, addresses on a bus in response to a cache injection instruction, wherein the cache injection instruction causes a cache controller to modify a grab coherency bit of a coherency status field included in a cache directory to indicate that cache injection is to be employed to provide input/output data to a data block of the cache that is associated with the grab co…
Physics · mapped topic
Physics · mapped topic
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