Synchronized debug information generation

Patent metadata

Field	Value
Publication number	US-9256489-B2
Application number	US-201314066722-A
Country	US
Kind code	B2
Filing date	Oct 30, 2013
Priority date	Oct 30, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

In an approach for determining a location of failure between interconnects/controller, a computer collects debug information simultaneously at a plurality of nodes coupled to an interconnect. Subsequent to collecting debug information, the computer analyzes the debug information collected simultaneously thereby determining which end of the interconnect caused the failure.

First claim

What is claimed is:

1. A computer program product for determining a location of failure between interconnects/controller, the computer program product comprising:
one or more computer-readable storage device and program instructions stored on the one or more computer-readable storage device, the stored program instructions comprising:
program instructions to collect debug information simultaneously at a plurality of nodes coupled to an interconnect; and
program instructions to analyze the debug information collected simultaneously thereby determining which end of the interconnect caused the failure.

2. The computer program product of claim 1 , further comprising:
program instructions to determine, by a first system controller coupled to a second system controller and a plurality of node controllers of a server computer, an error in the server computer;
program instructions to determine, by the first system controller, that a simultaneous dump should be performed by a plurality of both the second system controller and the plurality of node controllers, responsive to determining the error in the server computer; and
program instructions to perform, by the plurality of both the second system controller and the plurality of node controllers, the simultaneous dump.

3. The computer program product of claim 2 , further comprising program instructions to broadcast, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers, responsive to determining that the simultaneous dump should be performed.

4. The computer program product of claim 3 , wherein broadcasting, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers comprises program instructions to utilize a programmable interrupt generator in the server computer to communicate with the plurality of system controllers and the plurality of node controllers.

5. The computer program product of claim 3 , wherein broadcasting, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers comprises program instructions to broadcast, by the first system controller, the error on an ethernet transport on which the plurality of both the second system controller and the plurality of node controllers reside.

6. The computer program product of claim 3 , wherein broadcasting, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers comprises program instructions to utilize a functional subsystem interface (FSI) in the server computer to communicate with the plurality of system controllers and the plurality of node controllers.

7. The computer program product of claim 2 , wherein program instructions to determine, by the first system controller, that a simultaneous dump should be performed by a plurality of both the second system controller and the plurality of node controllers further comprise program instructions to utilize a predetermined map that defines scenarios for which a simultaneous dump is required.

8. A computer system for determining a location of failure between interconnects/controller, the computer system comprising:
one or more computer processors;
one or more computer-readable storage device;
program instructions stored on the computer-readable storage device for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to collect debug information simultaneously at a plurality of nodes coupled to an interconnect; and
program instructions to analyze the debug information collected simultaneously thereby determining which end of the interconnect caused the failure.

9. The computer system of claim 8 , further comprising:
program instructions to determine, by a first system controller coupled to a second system controller and a plurality of node controllers of a server computer, an error in the server computer;
program instructions to determine, by the first system controller, that a simultaneous dump should be performed by a plurality of both the second system controller and the plurality of node controllers, responsive to determining the error in the server computer; and
program instructions to perform, by the plurality of both the second system controller and the plurality of node controllers, the simultaneous dump.

10. The computer system of claim 9 , further comprising program instructions to broadcast, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers, responsive to determining that the simultaneous dump should be performed.

11. The computer system of claim 10 , wherein broadcasting, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers comprises program instructions to utilize a programmable interrupt generator in the server computer to communicate with the plurality of system controllers and the plurality of node controllers.

12. The computer system of claim 10 , wherein broadcasting, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers comprises program instructions to broadcast, by the first system controller, the error on an ethernet transport on which the plurality of both the second system controller and the plurality of node controllers reside.

13. The computer system of claim 9 , wherein program instructions to determine, by the first system controller, that a simultaneous dump should be performed by a plurality of both the second system controller and the plurality of node controllers further comprise program instructions to utilize a predetermined map that defines scenarios for which a simultaneous dump is required.

Assignees

• IBM

Inventors

• Mahajan Ajay K
• Sainath Venkatesh
• Subbanna Vishwanatha

Classifications

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F11/0778

  Dumping, i.e. gathering error/state information after a fault for later diagnosis · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title