Data link power reduction technique using bipolar pulse amplitude modulation

Patent metadata

Field	Value
Publication number	US-9252997-B1
Application number	US-201414328556-A
Country	US
Kind code	B1
Filing date	Jul 10, 2014
Priority date	Jul 10, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface.

First claim

What is claimed is:

1. An apparatus comprising:
a termination resistor configured to receive multi-level signaling and generate corresponding polarized voltages and currents according to an amplitude of received multi-level signaling;
a biasing source communicatively coupled to the termination resistor and configured to selectively generate a biasing-voltage level on the termination resistor; and
a multi-level decoder communicatively coupled across the termination resistor and configured to determine respective entries from a set of compound-index entries according to the polarized voltages and currents across the termination resistor and correspondingly retrieve an associated data symbol from an array of data symbols.

2. The apparatus of claim 1 , wherein the termination resistor is configured to receive a plurality of voltage levels corresponding to the received multi-level signaling and generate the corresponding polarized voltages and currents according to the combination of the multi-level signaling and the biasing-voltage level.

3. The apparatus of claim 1 , wherein the multi-level decoder includes:
a level decoder communicatively coupled across the termination resistor and configured to determine a first portion of the respective entries in the set of compound-index entries;
a current sensor communicatively coupled across the termination resistor and configured to determine a second portion of the respective entries in the set of compound-index entries; and
a lookup table communicatively coupled to the level decoder and the current sensor, the lookup table includes the array of data symbols and a corresponding index, the lookup table is configured to receive a respective entry from the set of compound-index entries and apply the entry to the index to retrieve the associated data symbol from the array of data symbols.

4. The apparatus of claim 3 , wherein the index is configured to uniquely associate the first portion and the second portion of one in the set of compound-index entries with an associated data symbol from the array of data symbols.

5. The apparatus of claim 3 , wherein the level decoder is configured to determine a voltage magnitude across the termination resistor during receipt of the multi-level signaling, further wherein each voltage magnitude determines a first portion of the respective entry in the set of compound-index entries.

6. The apparatus of claim 3 , wherein the current sensor is configured to determine a direction of current flowing through the termination resistor by measuring a polarity of the voltage across the termination resistor during receipt of the multi-level signaling.

7. The apparatus of claim 3 , further comprising a receiver memory communicatively coupled to the lookup table and configured to store data symbols corresponding to the multi-level signaling.

8. The apparatus of claim 1 , wherein an amount of power utilized in retrieving the data symbol from the array of data symbols according to a biasing-voltage level of about 33% of a maximum-amplitude-signaling level, is about 57% less than an amount of power utilized in retrieving a further data symbol from the array of data symbols with a biasing-voltage level 0V.

9. A method comprising:
applying a predetermined biasing-voltage level to a termination resistor communicatively coupled to a data-link terminal of a receiver;
receiving a pulse-amplitude-modulation signal according to a voltage level across the data-link terminal;
according to the receiving, measuring a voltage level across, and a current amplitude through the termination resistor;
according to the measuring, aggregating a compound index including the measured voltage level across and the measured current amplitude through the termination resistor;
selectively accessing a message symbol in a message symbol array within a multi-level decoder according to the compound index; and
retrieving the message symbol from the multi-level decoder according to the accessing.

10. The method of claim 9 , wherein method further comprising:
mapping the measured voltage level to a multi-level signaling amplitude;
mapping the measured current amplitude through the termination resistor to a current direction indicator;
aggregating the compound index further includes the multi-level signaling amplitude being a first portion and the measured current direction indicator being a second portion of the compound index; and
transmitting the retrieved message symbol to a receiver memory.

11. The method of claim 10 , wherein:
according to the multi-level signaling amplitude, the pulse-amplitude-modulation signal includes a range of voltage levels and
the adjusting includes selectively adjusting the magnitude of the biasing-voltage level between about one-third and one-half of a maximum-amplitude-signaling level in the range of voltage levels of the pulse-amplitude-modulation signal.

12. The method of claim 9 , wherein the message symbol is an inverted-data symbol, the method further comprising:
detecting an inversion indication associated with the inverted-data symbol, the inversion indication further associated with a partition of bits within the inverted-data symbol;
according to the inversion indication, selectively inverting the partition of bits within the inverted-data symbol to produce a data symbol; and
transmitting the data symbol to a receiver memory.

13. The method of claim 12 , wherein the inversion indication signifies that a most-significant partition of the inverted-data symbol is conditionally inverted according to an encoding process.

14. The method of claim 12 , wherein:
the inversion indication signifies that bits within the partition in the inverted-data symbol are inverted according to an encoding process and
the partition is specified within the encoding process.

15. The method of claim 12 , wherein the inversion indication is a binary bit situated within the inverted-data symbol at a bit location separate from a data-designating portion.

16. The method of claim 12 , wherein the data symbol includes a pulse-amplitude-modulation signal.

17. The method of claim 9 , wherein the message symbol is an inverted-data symbol, the method further comprising:
detecting an inversion indication associated with the inverted-data symbol;
decoding the inversion indication into a partition selector and an inversion designator;
determining a selected partition according to the partition selector, wherein an odd partition is selected when the partition selector is asserted, otherwise an even partition is determined to be selected;
selectively inverting bits within the selected partition according to the inversion designator, wherein bits within the selected partition are inverted when the inversion designator is asserted, otherwise bits within the selected partition are maintained; and
transmitting the data symbol to a receiver memory.

18. The method of claim 17 , wherein the decoding includes decoding the inversion indication into an ordered pair of binary bits including a first bit corresponding to the partition selector and a second bit corresponding to the inversion designator.

19. The method of claim 17 , wherein the inversion indication is a multi-level-inversion symbol encoded to include an ordered pair of binary bits, the ordered pair including a first bit corresponding to the partition selector and a second bit corresponding to the inversion designator.

20. The method of claim 19 , wherein the inversion indication is a multi-level-inversion s

Assignees

• Qualcomm Inc

Inventors

• Mishra Lalan Jee
• Hollis Timothy Mowry

Classifications

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04L25/4927 Primary

  using levels matched to the quantisation levels of the channel · CPC title

• H04L25/06

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title

• H04L25/0292 Primary

  Arrangements specific to the receiver end · CPC title

• H04L25/4915

  using pattern inversion or substitution (H04L25/4908 takes precedence) · CPC title