Bus communication transceiver

Patent metadata

Field	Value
Publication number	US-9252984-B2
Application number	US-201514690983-A
Country	US
Kind code	B2
Filing date	Apr 20, 2015
Priority date	Feb 4, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A semiconductor device including a bus communication transceiver configured to be adopted in an automobile, including a transmission circuit to receive an input signal from an input node and generate a transmission signal; a bus connection node to couple with an external single wire bus to transmit the transmission signal to the external single wire bus and to receive a reception signal from the external single wire bus, the external single wire bus being coupled with an on-board battery of the automobile; a reception circuit to receive the reception signal or the transmission signal from the single wire bus to generate an output signal; and a delay time measurement circuit to measure a delay time from a rising time of the input signal to a rising time of the output signal generated from the input signal, and to generate a delay time measurement result signal group.

First claim

What is claimed is:

1. A semiconductor device including a bus communication transceiver configured to be adopted in an automobile, comprising:
an input node configured to receive an input signal;
a transmission circuit configured to receive the input signal from the input node and to generate a transmission signal;
a bus connection node configured to couple with an external single wire bus to transmit the transmission signal to the external single wire bus and to receive a reception signal from the external single wire bus, the external single wire bus being coupled with an on-board battery of the automobile;
a reception circuit configured to receive the reception signal or the transmission signal from the single wire bus to generate an output signal;
an output node configured to output the output signal; and
a delay time measurement circuit configured to measure a delay time from a rising time of the input signal to a rising time of the output signal generated from the input signal, and to generate a delay time measurement result signal group showing the measurement results,
wherein the transmission circuit comprises an output waveform adjustment circuit configured to adjust a voltage inclination in a falling waveform of the transmission signal generated from the input signal, based on the delay time measurement result signal group.

2. The bus communication transceiver according to claim 1 , wherein the output waveform adjustment circuit comprises:
a current source circuit configured to supply currents with different current values based on the delay time measurement result signal group; and
an inverter circuit configured to receive the input signal and to output intermediate signals which have different voltage inclinations based on the currents supplied from the current source circuit,
wherein the transmission circuit further comprises:
an output circuit configured to generate the transmission signal from the intermediate signals.

3. The bus communication transceiver according to claim 2 , wherein the current source circuit comprises:
a main current source configured to supply a main current to the inverter circuit;
a plurality of sub-current sources configured to supply a plurality of sub-currents to the inverter circuit, respectively;
a plurality of switches connected with the plurality of sub-current sources in series, to carry out a switching operation to set states between a part or whole of the plurality of sub-currents and the inverter circuit to conductive states or blocking-off states.

4. The bus communication transceiver according to claim 3 , wherein the delay time measurement circuit comprises:
a buffer constant current source configured to supply a buffer current;
a buffer configured to receive the input signal and to output the voltage inclination based on the buffer current;
a capacitance connected with an output node of the buffer;
a plurality of resistances connected in series between a first power supply voltage and a second power supply voltage to generate a plurality of reference voltages generated by dividing a voltage between the first power supply voltage and the second power supply voltage;
a plurality of comparators configured to compare a voltage applied to the capacitance with the plurality of reference voltages, and to output the comparison result signal group indicating the comparison results; and
a latch circuit configured to latch the comparison result signal group at a time of rising of the output signal to output the latched signals as the delay time measurement result signal group.

5. The bus communication transceiver according to claim 3 , wherein the delay time measurement circuit comprises:
a plurality of buffer constant current sources to supply a plurality of buffer currents;
a plurality of buffers configured to receive the input signal and to output a plurality of voltage inclinations respectively corresponding to the plurality of buffer currents;
a plurality of capacitances connected with output nodes of the plurality of buffers, respectively;
a plurality of resistances connected in series between a first power supply voltage and a second power supply voltage, to generate reference voltages by dividing a voltage between the first power supply voltage and the second power supply voltage;
a plurality of comparators configured to respectively compare voltages applied to the plurality of the capacitances with the reference voltages and to output a comparison result signal group showing comparison results; and
a latch circuit configured to latch the comparison result signal group in response to a rising time of the output signal to output as a delay time measurement result signal group.

6. The bus communication transceiver according to claim 4 , wherein the latch circuit comprises:
a plurality of latches having input nodes connected with output nodes of the plurality of comparators, and output nodes connected with control signal input nodes of the plurality of switches, respectively.

7. The bus communication transceiver according to claim 4 , further comprising:
a switch configured to connect the plurality of resistances with the first or second power supply voltage during measurement of the delay time, and to disconnect the plurality of resistances from the first or second power supply voltage during a part or an entirety of a time period for which the measurement of the delay time is unnecessary.

8. The bus communication transceiver according to claim 6 , further comprising:
a switch configured to connect the plurality of resistances with the first or second power supply voltage during measurement of the delay time, and to disconnect the plurality of resistances from the first or second power supply voltage during a part or an entirety of a time period for which the measurement of the delay time is unnecessary.

9. A bus communication transceiver configured to be adopted in an automobile, comprising:
a transmission circuit configured to receive an input signal and to generate a transmission signal based thereon;
a bus connection node configured to couple with an external single wire bus to transmit the transmission signal to the external single wire bus and to receive a reception signal from the external single wire bus, the external single wire bus being coupled with an on-board battery of the automobile;
a reception circuit configured to receive the reception signal or the transmission signal from the single wire bus to generate an output signal; and
a delay time measurement circuit configured to measure a delay time from a rising time of the input signal to a rising time of the output signal generated from the input signal, and to generate a delay time measurement result signal group showing the measurement results,
wherein the transmission circuit comprises an output waveform adjustment circuit configured to adjust a voltage inclination in a falling waveform of the transmission signal generated from the input signal, based on the delay time measurement result signal group.

10. The bus communication transceiver according to claim 9 , further comprising:
an input node configured to receive the input signal and to provide the input signal to the transmission circuit.

11. The bus communication transceiver according to claim 9 , further comprising:
an output node configured to output the output signal.

12. The bus communication transceiver according to claim 9 , wherein the output waveform adjustment circuit comprises:
a current source circuit configured to supply currents with different current values based on the delay time measurement result signal group; and
an inverter circuit conf

Assignees

• Renesas Electronics Corp

Inventors

• Kiuchi Hideki

Classifications

• H04L25/026 Primary

  Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers (duplexing arrangements H04L5/14) · CPC title

• H04L7/00

  Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title

• H04L25/06

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title

• H03K6/04

  Modifying slopes of pulses, e.g. S-correction (S-correction in television H04N3/23) · CPC title