Link training and training frame for 100GBPS ethernet

Patent metadata

Field	Value
Publication number	US-9252968-B2
Application number	US-201213531145-A
Country	US
Kind code	B2
Filing date	Jun 22, 2012
Priority date	Jun 22, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Methods, apparatus and systems for implementing link training for next-generation high-speed Ethernet links including a 100 Gbps Ethernet link. Training frames are transmitted from a transmit port to be received at a receive port, with each training frame comprising a frame marker portion, a control channel portion, and a training pattern portion. Four-level signaling including a low level signal, first and second intermediate level signals, and a high level signal is implemented for the training pattern portion of the training frame using a pseudo-random bit pattern, while only the low and high level signals are employed for the frame marker and control channel portions of the training frame. The four-level signaling may employ PAM4 encoding. Examples of apparatus and systems in which the link training techniques may be implemented include blade servers and network routers and switches.

First claim

What is claimed is:

1. A method for link training for a high-speed Ethernet link, comprising:
transmitting training frames from a transmit port to be received at a receive port; each training frame comprising a frame marker portion, a control channel portion, and a training pattern portion and employing four-level pulse amplitude modulation (PAM4) signaling including a low level signal, a first intermediate level signal, a second intermediate level signal, and a high level signal;
employing four-level signaling for the training pattern portion of the training frame, the four-level signaling including the low level signal, the first intermediate level signal, the second intermediate level signal, and the high level signal; and
employing only the low and high level signals for the frame marker and control channel portions of the training frame,
wherein the high-speed Ethernet link employs a Physical layer including a Physical Media Attachment (PMA) sublayer that is configured to perform a plurality of adaptation processes including an overhead insertion process, a termination process, a Gray coding process, a precoding process and a PAM4 encoding process, and wherein the training pattern data corresponding to the training pattern portion of the training frame is generated in a manner that bypasses the overhead insertion process in the PMA sublayer.

2. The method of claim 1 , further comprising generating frame marker data corresponding to the frame marker portion of the training frame in a manner that bypasses the overhead process, the termination process, the Gray coding process, and the precoding process in the PMA sublayer.

3. The method of claim 1 , further comprising generating control channel data corresponding to the control channel portion of the training frame in a manner that bypasses the overhead process, the termination process, the Gray coding process, and the precoding process in the PMA sublayer.

4. The method of claim 1 , further comprising employing a Pseudo-Random Bit Sequence (PRBS) bit pattern for a first portion of the training pattern and employing an inversion of the PRBS bit pattern for a second portion of the training pattern.

5. The method of claim 4 , wherein the PRBS bit pattern comprises a PRBS12 12-bit pattern.

6. The method of claim 5 , wherein a PRBS12 initial state is selected from among PRBS12 initial states that are Direct Current (DC) balanced when used with a termination process, a Gray coding process, a precoding process and a four-level pulse amplitude modulation (PAM4) encoding process and for which the final state of a precoder operation is ‘0’.

7. The method of claim 6 , wherein the Ethernet link comprises a multi-lane link employing four lanes, and PRBS12 initial states are selected for respective lanes such the PRBS12 initial states are approximately ¼ cycle apart from one another.

8. The method of claim 1 , further comprising:
employing at least a portion of cell fields in the control channel portion of the training frame that are compatible with the Institute of Electrical and Electronics Engineers (IEEE) 10GBASE-KR PHY specification.

9. The method of claim 1 , wherein the training frame comprises a plurality of training frame words have a length of 46 Unit Intervals (UIs).

10. The method of claim 9 , wherein at least a portion of the training frame words include a plurality of bits that are implemented as parity bits.

11. The method of claim 10 , wherein the control channel portion of the training frame includes a coefficient update portion and a status report portion, and wherein separate parity bits are employed for each of the coefficient update portion and the status report portion.

12. The method of claim 1 , wherein the Ethernet link comprises a multi-lane link including multiple lanes, further comprising transmitting training frames over each of multiple lanes.

13. The method of claim 1 , wherein the Ethernet link comprises a physical media implemented via wiring in one of a mid-plane or back-plane.

14. The method of claim 1 , wherein the high-speed Ethernet port supports a bandwidth of 100 Gigabits per second.

15. An apparatus including a high-speed Ethernet transmit port configured to perform operations when the apparatus is operating comprising:
transmitting training frames from the transmit port to be received at a receive port; each training frame comprising a frame marker portion, a control channel portion, and a training pattern portion and employing four-level pulse amplitude modulation (PAM4) signaling including a low level signal, a first intermediate level signal, a second intermediate level signal, and a high level signal;
employing four-level signaling for the training pattern portion of the training frame, the four-level signaling including the low level signal, the first intermediate level signal, the second intermediate level signal, and the high level signal; and
employing only the low and high level signals for the frame marker and control channel portions of the training frame,
wherein the high-speed Ethernet link employs a Physical layer including a Physical Media Attachment (PMA) sublayer that is configured to perform a plurality of adaptation processes including an overhead insertion process, a termination process, a Gray coding process, a precoding process and a PAM4 encoding process, and wherein the training pattern data corresponding to the training pattern portion of the training frame is generated in a manner that bypasses the overhead insertion process in the PMA sublayer.

16. The apparatus of claim 15 , wherein the high-speed Ethernet transmit port is configured to generate frame marker data and control channel data corresponding to the frame marker portion and the control channel portion of the training frame in a manner that bypasses the overhead process, the termination process, the Gray coding process, and the precoding process in the PMA sublayer.

17. The apparatus of claim 15 , wherein the high-speed Ethernet transmit port is configured to employ a Pseudo-Random Bit Sequence (PRBS) bit pattern for a first portion of the training pattern and an inversion of the PRBS bit pattern for a second portion of the training pattern.

18. The apparatus of claim 15 , wherein the high-speed Ethernet transmit port is configured to employ at least a portion of cell fields in the control channel portion of the training frame that are compatible with the Institute of Electrical and Electronics Engineers (IEEE) IEEE 10GBASE-KR PHY specification.

19. The apparatus of claim 15 , wherein the high-speed Ethernet transmit port is configured to implement a multi-lane link including multiple lanes, and the Ethernet transmit port is further configured to transmit training frames over each of multiple lanes.

20. The apparatus of claim 15 , wherein the high-speed Ethernet transmit port supports a bandwidth of 100 Gigabits per second.

21. The apparatus of claim 15 , further comprising a high-speed Ethernet receive port configured to receive training frames from a second apparatus.

22. A system comprising:
a chassis;
an inter-plane, mounted within the chassis, having first and second inter-plane connectors and wiring coupled there between configured to facilitate a 100 Gigabits per second (Gbps) Ethernet link;
a first board having a first network interface controller (NIC) including 100 Gbps Ethernet transmit and receive ports operatively coupled to a first board connector that is coupled to the first inter-plane connector;

Assignees

• Lusted Kent C
• Ran Adee O
• Intel Corp

Inventors

• Lusted Kent C
• Ran Adee O

Classifications

• H04L12/413 Primary

  with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L1/0061

  Error detection codes · CPC title

• H04L1/0072

  Error control for data other than payload data, e.g. control data · CPC title