Die-to-die communication links for receiver integrated circuit dies and related methods

US9252891B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9252891-B2
Application numberUS-201414575391-A
CountryUS
Kind codeB2
Filing dateDec 18, 2014
Priority dateNov 7, 2013
Publication dateFeb 2, 2016
Grant dateFeb 2, 2016

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  2. Abstract

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Abstract

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Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that the operation of receive path circuitry can be adjusted without requiring intervention from an external host processor integrated circuit. A variety of operating parameter information can be communicated through the die-to-die communication links so that the integrated circuit dies can quickly adjust to changing signal conditions without requiring intervention by the external host processor integrated circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A multi-die system having die-to-die communications, comprising: a first integrated circuit die, comprising: a radio frequency (RF) input configured to receive an RF input signal; receive path circuitry coupled to receive the RF input signal and configured to generate a tuned digital signal representing content of a channel within the RF input signal based upon a channel selection signal, the receive path circuitry including analog front end circu…

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What does patent US9252891B2 cover?
Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that …
Who is the assignee on this patent?
Silicon Lab Inc
What technology area does this patent fall under?
Primary CPC classification H04B15/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).