Memory system and method of controlling memory system

Patent metadata

Field	Value
Publication number	US-9252810-B2
Application number	US-201414445229-A
Country	US
Kind code	B2
Filing date	Jul 29, 2014
Priority date	Feb 20, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

According to one embodiment, a controller writes first write data transferred from a first buffer and code data for second write data different from the first write data, the code data being transferred from a second buffer, in parallel to a plurality of physical pages corresponding to a first logical page. The controller writes code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile memory having a plurality of memory units capable of parallel operations, each of the memory units having a plurality of physical blocks, each of the physical blocks being a unit of data erasing, each of the physical blocks having a plurality of physical pages;
a first buffer that buffers therein write data from a host device;
an ECC processing unit that creates code data from write data buffered in the first buffer;
a second buffer that buffers therein the code data created by the ECC processing unit; and
a controller configured to
associate physical blocks selected from each of the memory units capable of parallel operations with one logical block, the logical block including a plurality of logical pages,
associate each of the logical pages with a plurality of physical pages having a same page number,
write first write data transferred from the first buffer and the code data for second write data different from the first write data, the code data being transferred from the second buffer, in parallel to the plurality of physical pages corresponding to a first logical page, and
write the code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.

2. The memory system according to claim 1 , wherein the ECC processing unit snoops write data to be transferred from the first buffer and creates code data using the snooped write data.

3. The memory system according to claim 1 , wherein the code data is stored to be distributed to the plurality of memory units.

4. The memory system according to claim 1 , wherein the code data is fixedly stored in one of the memory units.

5. The memory system according to claim 1 , wherein an ECC method adopted in the ECC processing unit generates a cyclic code.

6. The memory system according to claim 1 , wherein in an ECC method adopted in the ECC processing unit, a parity is calculated by an exclusive OR.

7. The memory system according to claim 1 , wherein each of the first buffer and the second buffer is a DRAM, a SRAM, or a cache area in the nonvolatile memory.

8. A method of controlling a memory system, the memory system including
a nonvolatile memory having a plurality of memory units capable of parallel operations, each of the memory units having a plurality of physical blocks, each of the physical blocks being a unit of data erasing, each of the physical blocks having a plurality of physical pages,
a first buffer, and
a second buffer, the method comprising
buffering write data from a host device to the first buffer,
creating code data from the write data buffered in the first buffer and buffering the code data to the second buffer,
associating physical blocks selected from each of the memory units capable of parallel operations with one logical block, the logical block including a plurality of logical pages,
associating each of the logical pages with a plurality of physical pages having a same page number,
writing first write data transferred from the first buffer and the code data for second write data different from the first write data, the code data being transferred from the second buffer, in parallel to the plurality of physical pages corresponding to a first logical page, and
writing the code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.

9. The method of controlling a memory system according to claim 8 , further comprising snooping write data to be transferred from the first buffer and creating code data using snooped write data.

10. The method of controlling a memory system according to claim 8 , wherein the code data is stored to be distributed to the plurality of memory units.

11. The method of controlling a memory system according to claim 8 , wherein the code data is fixedly stored in one of the memory units.

12. The method of controlling a memory system according to claim 8 , wherein the code data is a cyclic code data.

13. The method of controlling a memory system according to claim 8 , wherein the code data is a parity data calculated by an exclusive OR.

14. The method of controlling a memory system according to claim 8 , wherein each of the first buffer and the second buffer is a DRAM, a SRAM, or a cache area in the nonvolatile memory.

Assignees

• Toshiba Kk

Inventors

• Fukuda Tohru

Classifications

• H03M13/6566

  Implementations concerning memory access contentions · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• H03M13/05 Primary

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• H03M13/2707 Primary

  Simple row-column interleaver, i.e. pure block interleaving · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title