Apparatus and method for preventing multiple resets

Patent metadata

Field	Value
Publication number	US-9252751-B2
Application number	US-201414269194-A
Country	US
Kind code	B2
Filing date	May 4, 2014
Priority date	May 4, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.

First claim

The invention claimed is:

1. An apparatus for preventing multiple resets in an integrated circuit device, the apparatus comprising:
a voltage comparator for monitoring a supply voltage level and comparing said supply voltage level with a reference voltage level, generating an enable signal when the supply voltage level reaches a first reference voltage level, and generating a clear signal when the supply voltage level drops below a second reference voltage level;
a latch arrangement for latching at least one trim value and having a first input for receiving at least one trim value from the integrated circuit device, wherein a trim value relates to at least one of a voltage regulator and a low voltage detector, a second input for receiving a load trim value instruction from the integrated circuit device, a third input for receiving the enable and clear signals from the voltage comparator, and an output for connection to at least one of a voltage regulator and low voltage detector,
wherein the latch arrangement latches and transfers received trim values to its output upon receipt of said instruction and of a generated enable signal, and clears the latched values from its output upon receipt of a clear signal.

2. The apparatus of claim 1 , wherein the latch arrangement comprises a master/slave flip-flop with reset.

3. An integrated circuit including an apparatus for preventing multiple resets in said integrated circuit, the apparatus comprising:
a voltage comparator for monitoring a supply voltage level and comparing said supply voltage level with a reference voltage level, generating an enable signal when the supply voltage level reaches a first reference voltage level, and generating a clear signal when the supply voltage level drops below a second reference voltage level; and
a latch arrangement for latching at least one trim value and having a first input for receiving at least one trim value from the integrated circuit device wherein a trim value relates to at least one of a voltage regulator and a low voltage detector, a second input for receiving a load trim value instruction from the integrated circuit, a third input for receiving the enable and clear signals from the voltage comparator and an output for connection to at least one of a voltage regulator and low voltage detector,
wherein the latch arrangement latches and transfers received trim values to its output upon receipt of said instruction and of a generated enable signal, and clears the latched values from its output on receipt of a clear signal.

4. The integrated circuit of claim 3 , wherein the integrated circuit is a system-on-chip.

5. The integrated circuit of claim 3 , further comprising at least one of a voltage regulator and a low voltage detector and wherein the output of the voltage comparator is coupled to an enable/disable input of said at least one of a voltage regulator and a low voltage detector.

6. The integrated circuit of claim 3 , further comprising a low voltage detector arranged to receive trim values from the latch arrangement, and a reset controller arranged to generate a reset signal in response to an output signal from the low voltage detector.

7. The integrated circuit of claim 6 , further comprising a counter coupled to the reset controller for counting a number of times the integrated circuit is reset.

8. The integrated circuit of claim 3 , further comprising a register for storing trim values.

9. The integrated circuit of claim 8 , further comprising at least one level shifter for receiving a trim value stored in the register and for transferring said trim value to the latch arrangement.

10. The integrated circuit of claim 3 , further comprising a flash memory for holding trim values.

11. The integrated circuit of claim 3 , further comprising a fuse for holding trim values.

12. A method for preventing multiple resets in an integrated circuit device, wherein the integrated circuit device includes a power controller, the method comprising:
monitoring, in the power controller, a supply voltage level and comparing the supply voltage level with a reference voltage level;
generating an enable signal when the supply voltage level reaches a first reference voltage level and generating a clear signal when the supply voltage level drops below a second reference voltage level;
receiving a load trim value instruction from the integrated circuit device, wherein a trim value relates to at least one of a voltage regulator and a low voltage detector;
latching the trim value upon receipt of the instruction and a generated enable signal; and
clearing the latched trim value upon receipt of a clear signal when the supply voltage level falls below the second reference voltage level.

13. The method of claim 12 , further comprising generating, in the integrated circuit device, a load trim value instruction.

14. The method of claim 13 , further comprising storing trim values in a trim register and latching the trim values from the trim register in a test mode of operation.

Assignees

• Thakur Nishant Singh
• Pandey Rakesh
• Rana Manmohan
• Freescale Semiconductor Inc

Inventors

• Thakur Nishant Singh
• Pandey Rakesh
• Rana Manmohan

Classifications

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H03K17/223

  in field-effect transistor switches · CPC title