Phase noise reduction in LC-VCO

Patent metadata

Field	Value
Publication number	US-9252717-B2
Application number	US-201414295794-A
Country	US
Kind code	B2
Filing date	Jun 4, 2014
Priority date	Jun 4, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.

First claim

What is claimed is:

1. A transconductance cell for use in a voltage controlled oscillator (VCO), comprising:
a first NFET stack connected in series to a first PFET stack; and
a second NFET stack connected in series to a second PFET stack,
wherein the first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack;
the first NFET stack and the second NFET stack are connected to a tail node; and
the first PFET stack and the second PFET stack are connected to a power supply node;
wherein the first NFET stack comprises a first NFET and a second NFET;
the second NFET stack comprises a third NFET and a fourth NFET;
the first PFET stack comprises a first PFET and a second PFET; and
the second PFET stack comprises a third PFET and a fourth PFET.

2. The transconductance cell of claim 1 , wherein:
the first NFET is connected to the tail node;
the third NFET is connected to the tail node;
the first PFET is connected to the second NFET;
the second PFET is connected to the power supply node;
the third PFET is connected to the fourth NFET; and
the fourth PFET is connected to the power supply node.

3. The transconductance cell of claim 2 , wherein:
respective gates of the first NFET, the second NFET, the first PFET and the second PFET are connected to a drain of the fourth NFET and a drain of the third PFET; and
respective gates of respective gates of the third NFET, the fourth NFET, the third PFET and the fourth PFET are connected to a drain of the second NFET and a drain of the first PFET.

4. The transconductance cell of claim 3 , wherein:
a drain of the first NFET is connected to a source of the second NFET;
a drain of the third NFET is connected to a source of the fourth NFET;
a source of the first PFET is connected to a drain of the second PFET; and
a source of the third PFET is connected to a drain of the fourth PFET.

5. The transconductance cell of claim 3 , wherein:
the respective gates of the first NFET, the second NFET, the first PFET and the second PFET are structured and arranged to be connected to a first node of the VCO; and
the respective gates of respective gates of the third NFET, the fourth NFET, the third PFET and the fourth PFET are structured and arranged to be connected to a second node of the VCO.

6. The transconductance cell of claim 1 , wherein:
the tail node is connected to ground by a switch; and
the power supply node is connected to a rail voltage.

7. The transconductance cell of claim 1 , wherein:
gates of transistors in the first NFET stack and the first PFET stack are structured and arranged to be connected to a first node in the VCO; and
gates of transistors in the second NFET stack and the second PFET stack are structured and arranged to be connected to a second node in the VCO.

8. The transconductance cell of claim 1 , wherein the transconductance cell is structured and arranged to be connected between a first node and a second node of the VCO in parallel with an inductor and a varactor that are connected between the first node and the second node.

9. A transconductance cell for use in a voltage controlled oscillator (VCO), comprising:
a first NFET stack connected in series to a first PFET stack; and
a second NFET stack connected in series to a second PFET stack,
wherein the first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack;
the first NFET stack and the second NFET stack are connected to a tail node; and
the first PFET stack and the second PFET stack are connected to a power supply node,
wherein transistors of the first NFET stack, the first PFET stack, the second NFET stack, and the second PFET stack are sized to provide a same transconductance and a reduced phase noise relative to another transconductance cell that includes only non-stacked transistors.

10. A voltage controlled oscillator, comprising:
an inductor connected between a first node and a second node;
at least one varactor connected between the first node and the second node; and
a transconductance cell connected between the first node and the second node, wherein the transconductance cell comprises:
a first NFET set connected in series to a first PFET set; and
a second NFET set connected in series to a second PFET set,
wherein the first NFET set and the first PFET set are cross-coupled to the second NFET set and the second PFET set;
the first NFET set and the second NFET set are connected to a tail node that is selectively switched to ground;
the first PFET set and the second PFET set are connected to a power supply node; and
at least one of: the first NFET set and the second NFET set each comprises a pair of stacked NFETs, and the first PFET set and the second PFET set each comprises a pair of stacked PFETs.

11. The voltage controlled oscillator of claim 10 , wherein:
the first NFET set comprises only a first NFET;
the second NFET set comprises only a second NFET;
the first PFET set comprises a first PFET stacked in series with a second PFET; and
the second PFET set comprises a third PFET stacked in series with a fourth PFET.

12. The voltage controlled oscillator of claim 10 , wherein:
the first PFET set comprises only a first PFET;
the second PFET set comprises only a second PFET;
the first NFET set comprises a first NFET stacked in series with a second NFET; and
the second NFET set comprises a third NFET stacked in series with a fourth NFET.

13. The voltage controlled oscillator of claim 10 , wherein the at least one varactor comprises:
a first varactor that receives a first portion of a differential control voltage; and
a second varactor that receives a second portion of a differential control voltage.

14. The voltage controlled oscillator of claim 10 , wherein the inductor, the at least one varactor, and the transconductance cell are connected in parallel between the first node and the second node.

15. The voltage controlled oscillator of claim 10 , wherein transistors of the first NFET set, the first PFET set, the second NFET set, and the second PFET set are sized to provide a same transconductance and a reduced phase noise relative to another transconductance cell that includes only non-stacked transistors.

16. A method, comprising:
fabricating a transconductance cell for use in a voltage controlled oscillator (VCO), wherein the transconductance cell comprises:
a first NFET stack connected in series to a first PFET stack; and
a second NFET stack connected in series to a second PFET stack,
wherein the first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack;
the first NFET stack and the second NFET stack are connected to a tail node that is selectively connected to ground by a switch; and
the first PFET stack and the second PFET stack are connected to a power supply node that supplies a rail voltage.

17. The method of claim 16 , further comprising:
determining a transconductance of another transconductance cell that includes only non-stacked transistors; and
sizing transistors of the first NFET stack, the first PFET stack, the second NFET stack, and the second PFET stack to provide a same transconductance and a reduced phase noise relative to the other transconductance cell.

18. The method of claim 16 , wherein the fabricating comprises:
forming the first NFET stack with a first NFET and a second NFET;
forming the second NFET stack with a third NFET and a fourth NFET;
forming the first PFET stack with

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Bonaccio Anthony R
• Jin Zhenrong
• Kelkar Ram
• Malladi Anjali R
• Malladi Ramana M

Classifications

• H03B5/10

  active element in amplifier being vacuum tube (H03B5/14 takes precedence) · CPC title

• H03B5/1228

  the amplifier comprising one or more field effect transistors · CPC title

• H03B5/1225

  the generator comprising multiple amplifiers connected in parallel · CPC title

• H03B5/34

  active element in amplifier being vacuum tube (H03B5/38 takes precedence) · CPC title

• H03B5/1212

  the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair · CPC title