Display substrate and method of manufacturing a display substrate

Patent metadata

Field	Value
Publication number	US-9252284-B2
Application number	US-201414182989-A
Country	US
Kind code	B2
Filing date	Feb 18, 2014
Priority date	Sep 2, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

First claim

What is claimed is:

1. A display substrate, comprising:
a substrate;
a gate electrode disposed on the substrate;
an active pattern comprising an oxide semiconductor, the active pattern comprising a first region, a second region, and a third region, the first region of the active pattern overlapping the gate electrode and having an electrical conductivity smaller than those of the second region and the third region;
a first insulation layer pattern and a second insulation layer pattern disposed on the first region of the active pattern, the first insulation layer pattern and the second insulation layer pattern overlapping the gate electrode; and
a third insulation layer covering the active pattern, the first insulation layer pattern, and the second insulation layer pattern, contacting the second region and the third region and being separated from the first region, and the third insulation layer comprising at least one of silicon nitride and silicon oxy-nitride,
wherein either the first insulation layer pattern or the second insulation layer pattern comprises aluminum oxide, and
wherein each of the first insulation layer pattern and the second insulation layer pattern has a width substantially the same as a width of the gate electrode.

2. The display substrate of claim 1 , wherein the first region of the active pattern has a width substantially the same as the width of the first insulation layer pattern.

3. The display substrate of claim 1 , wherein the second region and the third region of the active pattern are self-aligned to not overlap the gate electrode.

4. The display substrate of claim 1 , wherein the first insulation layer pattern and the second insulation layer pattern reduce a diffusion or a doping of the impurities from the third insulation layer into the first region of the active pattern.

5. The display substrate of claim 1 , further comprising a fourth insulation layer pattern disposed on the second insulation layer pattern.

6. The display substrate of claim 1 , further comprising a gate insulation layer disposed between the gate electrode and the active pattern.
wherein the active pattern comprises at least one of amorphous zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jong-Chan
• Khang Yoon-Ho
• Kang Su-Hyoung
• Kim Dong-Jo
• Lee Ji-Seon
• Cha Myoung-Geun
• Ji Deuk-Myung

Classifications

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6704 Primary

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title