MOSFET and method for manufacturing the same

US9252280B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9252280-B2
Application numberUS-201113510461-A
CountryUS
Kind codeB2
Filing dateNov 18, 2011
Priority dateSep 16, 2011
Publication dateFeb 2, 2016
Grant dateFeb 2, 2016

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Abstract

Official abstract text for this publication.

The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate.

First claim

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We claim: 1. A Metal Oxide Semiconductor Field Effect Transistor (MOSFET), comprising: a Semiconductor on Insulator (SOI) wafer, which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on op…

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What does patent US9252280B2 cover?
The present disclosure discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for manufacturing the same. The MOSFET includes: a silicon on insulator (SOI) wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the bu…
Who is the assignee on this patent?
Zhu Huilong, Xu Miao, Liang Qingqing, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10D30/6706. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).