Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9252261-B2
Application number	US-201214112097-A
Country	US
Kind code	B2
Filing date	Feb 24, 2012
Priority date	Apr 19, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

An anode region 106 is formed on a bottom portion of a trench 105 in which a gate electrode 108 is formed or in a drift region 102 immediately under the trench 105 . A contact hole 110 is formed in the trench 105 at a depth reaching the anode region 106 . A source electrode 112 is embedded in the contact hole 110 while interposing an inner wall insulating film 111 therebetween. The anode region 106 and the source electrode 112 are electrically connected to each other in a state of being insulated from the gate electrode 108 by the inner wall insulating film 111.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a drift region of first conductivity type formed on one of main surfaces of the semiconductor substrate;
a well region of second conductivity type formed in the drift region;
a source region of first conductivity type formed in the well region;
a trench with a depth penetrating the source region and the well region and reaching the drift region;
a gate electrode formed on a side portion of the trench while interposing a gate insulating film therebetween;
a source electrode connected to the well region and the source region;
a drain electrode connected to other of the main surfaces of the semiconductor substrate;
an interlayer insulating film that is formed on the gate electrode and coats the gate electrode;
an anode region formed on a bottom portion of the trench or in the drift region immediately under the trench;
a contact hole formed in the trench at a depth reaching the anode region; and
an inner wall insulating film formed on an inner wall side surface of the contact hole while being in contact with the gate electrode,
wherein the source electrode is embedded in the contact hole while interposing the inner wall insulating film between the source electrode and the gate electrode, and is electrically connected to the anode region in a state of being insulated from the gate electrode by the inner wall insulating film, and
a plurality of contact holes is formed discretely in the trench with respect to a main surface direction of the semiconductor substrate, and a width of the trench at portions in which the contact holes are formed is wider than a width of the trench at portions in which the contact holes are not formed.

2. The semiconductor device according to claim 1 , wherein the anode region is formed as a second conductivity type region in the drift region, and composes a PN junction-type diode on a junction surface with the drift region, the PN junction-type diode using the drift region as a cathode.

3. The semiconductor device according to claim 1 , wherein the anode region is formed of a material different from the drift region on the bottom portion of the trench, and composes a unipolar diode on a junction surface with the drift region.

4. The semiconductor device according to claim 3 , wherein the anode region is formed of a semiconductor different in band gap from the drift region.

5. The semiconductor device according to claim 1 , wherein a plurality of the trenches is formed linearly with respect to the main surface direction of the semiconductor substrate, and a plurality of the contact holes is formed discretely in the trenches with respect to the main surface direction of the semiconductor substrate, and the contact holes formed in the trenches adjacent to one another are arranged and formed alternately so as not to be opposite to one another.

6. A semiconductor device comprising:
a semiconductor substrate;
a drift region of first conductivity type formed on one of main surfaces of the semiconductor substrate;
a well region of second conductivity type formed in the drift region;
a source region of first conductivity type formed in the well region;
a trench with a depth penetrating the source region and the well region and reaching the drift region;
a gate electrode formed on a side portion of the trench while interposing a gate insulating film therebetween;
a source electrode connected to the well region and the source region;
a drain electrode connected to other of the main surfaces of the semiconductor substrate;
an interlayer insulating film that is formed on the gate electrode and coats the gate electrode;
an anode region formed on a bottom portion of he trench or in the drift region immediately under the trench;
a contact hole formed in the trench at a depth reaching the anode region; and
an inner wall insulating film formed on an inner wall side surface of the contact hole while being in contact with the gate electrode,
wherein the source electrode is embedded in the contact hole while interposing the inner wall insulating film between the source electrode and the gate electrode, and is electrically connected to the anode region in a state of being insulated from the gate electrode by the inner wall insulating film,
the anode region is formed of a semiconductor different in band gap from the drift region, and
a plurality of contact holes is formed discretely in the trench with respect to a main surface direction of the semiconductor substrate.

7. The semiconductor device according to claim 6 , wherein a plurality of trenches is formed into a mesh shape with respect to the main surface direction of the semiconductor substrate, and the plurality of contact holes is arranged and formed discretely on mesh intersections of the trenches.

8. The semiconductor device according to claim 6 , wherein the trench is formed linearly with respect to a main surface direction of the semiconductor substrate, and the contact holes are formed linearly along an inside of the trench.

9. The semiconductor device according to claim 6 , wherein the trench is formed into a mesh shape with respect to a main surface direction of the semiconductor substrate, and the contact holes are formed into a mesh shape along an inside of the trench.

Assignees

• Yamagami Shigeharu
• Hayashi Tetsuya
• Shimomura Taku
• Nissan Motor

Inventors

• Yamagami Shigeharu
• Hayashi Tetsuya
• Shimomura Taku

Classifications

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D84/143 Primary

  the built-in components being PN junction diodes · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/146

  the built-in components being Schottky barrier diodes · CPC title