Partially-blocked well implant to improve diode ideality with SiGe anode

Patent metadata

Field	Value
Publication number	US-9252234-B2
Application number	US-201213605290-A
Country	US
Kind code	B2
Filing date	Sep 6, 2012
Priority date	Sep 6, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
doping a p-type substrate to form an N-well from one portion of the p-type substrate adjacent an anode region from another portion of the p-type substrate, wherein an interface between the N-well and the anode extends vertically from a top surface of the p-type substrate to a bottom surface of the p-type substrate;
etching a cavity to a selected depth in the anode region adjacent the N-well;
depositing p-type doped material in the cavity to form a p-type doped region adjacent the N-well, wherein the interface between the N-well and the anode provides a sidewall boundary of the p-type material and a p-n junction associated with the p-type doped region extends into the N-well and into the anode region; and
forming a gate stack on the N-well having a spacer, wherein an outer sidewall of the gate stack is aligned with the vertical interface between the N-well and the anode.

2. The method of claim 1 , wherein doping the p-type substrate further comprises performing one of ion diffusion and ion implantation on a selected portion of the p-type substrate.

3. The method of claim 1 , further comprising selectively covering the anode region with a photoresist layer prior to doping the p-type substrate.

4. The method of claim 1 , wherein the N-well extends from an ion implantation surface of the substrate to a surface opposite the ion implantation surface of the substrate.

5. The method of claim 1 , wherein the semiconductor device further includes a semiconductor diode.

6. The method of claim 1 , further comprising forming the semiconductor device on an integrated chip.

7. The method of claim 1 , further comprising forming an electronic component at a surface of the substrate.

8. The method of claim 1 , further comprising forming an n-type doped region in the N-well.

9. The method of claim 8 , wherein the p-type doped region includes silicon germanium and the n-type doped region include silicon carbon.

10. A method of manufacturing a diode, comprising:
forming a photoresist layer over a p-type substrate to selectively cover a portion of the p-type substrate and leave exposed another portion of the p-type substrate;
forming an N-well at the exposed portion of the p-type substrate, wherein the covered portion forms an anode region such that an interface between the N-well and the anode extends vertically from a top surface of the P-type substrate to a bottom surface of the p-type substrate;
etching a cavity to a selected depth in the anode region adjacent the N-well;
depositing p-type doped material in the cavity to form a p-type doped region adjacent the N-well, wherein the interface between the N-well and the anode provides a sidewall boundary of the p-type material and a p-n junction associated with the p-type doped region extends into the N-well and into the anode region; and
forming a gate stack on the N-well having a spacer, wherein an outer sidewall of the gate stack is aligned with the vertical interface between the N-well and the anode.

11. The method of claim 10 , further comprising forming the N-well via one of ion diffusion and ion implantation at the exposed portion of the p-type substrate.

12. The method of claim 10 , wherein the N-well extends from an ion implantation surface of the substrate to a surface opposite the ion implantation surface of the substrate.

13. The method of claim 10 , further comprising forming an electronic component at a surface of the substrate.

14. The method of claim 10 , further comprising forming the diode from a substrate on an integrated chip.

15. A method of manufacturing a diode, comprising:
forming an anode and an N-well on a p-type substrate by partially blocking the substrate during ion doping, wherein an interface between the N-well and the anode extends vertically from a top surface of the P-type substrate to a bottom surface of the p-type substrate;
etching a cavity to a selected depth in the anode region adjacent the N-well;
depositing p-type doped material in the cavity to form an extrinsically p-type doped region adjacent the N-well, wherein the interface between the N-well and the anode provides a sidewall boundary of the p-type material and a p-n junction associated with the p-type doped region extends into the N-well and into the anode region; and
forming a gate stack on the N-well having a spacer, wherein an outer sidewall of the gate stack is aligned with the vertical interface between the N-well and the anode.

16. The method of claim 15 , further comprising forming the N-well via one of ion implantation and ion diffusion.

17. The method of claim 15 , further comprising forming an electronic component at a surface of the substrate.

Assignees

• Guo Dechao
• Haensch Wilfried E
• Wang Gan
• Wang Yanfeng
• Wang Xin
• IBM

Inventors

• Guo Dechao
• Haensch Wilfried E
• Wang Gan
• Wang Yanfeng
• Wang Xin

Classifications

• H10D12/211

  Gated diodes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D12/021 Primary

  of gated diodes, e.g. field-controlled diodes [FCD] · CPC title

• H01L29/1608

  Electricity · mapped topic