Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9252230-B2
Application number	US-201314055446-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Jul 3, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A semiconductor device and a method of manufacturing the same are provided. The device includes insulating patterns and conductive patterns stacked alternately, a channel layer formed through the insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of the channel layer, and a charge storage layer formed to surround the tunnel insulating layer. An interfacial surface of the tunnel insulating layer in contact with the charge storage layer includes a thermal oxide layer.

First claim

What is claimed is:

1. A semiconductor memory device comprising: insulating patterns and conductive patterns stacked alternately; a channel layer formed through the insulating patterns and the conductive patterns; a tunnel insulating layer formed to surround sidewalls of the channel layer; a charge storage layer formed to surround the tunnel insulating layer; and a blocking insulating layer formed to surround the charge storage layer, wherein the tunnel insulating layer includes a first tunnel insulating layer formed of a thermal oxide layer and a second tunnel insulating layer formed between the first tunnel insulating layer and the channel layer, wherein a surface of the first tunnel insulating layer is in contact with the charge storage layer.

2. The device of claim 1 , wherein the second tunnel insulating layer includes a radical oxide layer.

3. The device of claim 1 , wherein the second tunnel insulating layer is formed of at least one of a radical oxide layer, a dry oxide layer, and a wet oxide layer.

4. The device of claim 1 , wherein the thermal oxide layer is formed between the charge storage layer and the second tunnel insulating layer to prevent a SiON layer from being formed on the surface of the charge storage layer due to the second tunnel insulating layer.

5. A semiconductor memory device comprising: insulating patterns and conductive patterns stacked alternately; a channel layer formed through the insulating patterns and the conductive patterns; a first tunnel insulating layer formed to surround sidewalls of the channel layer; a second tunnel insulating layer formed to surround the first tunnel insulating layer; a charge storage layer formed to surround the second tunnel insulating layer; and a blocking insulating layer formed to surround the charge storage layer, wherein the second tunnel insulating layer includes a thermal oxide layer, and a surface of the second tunnel insulating layer is in contact with the charge storage layer.

6. The device of claim 5 , wherein the first tunnel insulating layer includes a radical oxide layer.

7. The device of claim 5 , wherein the first tunnel insulating layer is formed of at least one of a radical oxide layer, a dry oxide layer, and a wet oxide layer.

8. The device of claim 5 , wherein the second tunnel insulating layer is formed to prevent a SiON layer from being formed on the surface of the charge storage layer due to the first tunnel insulating layer.

9. A method of manufacturing a semiconductor memory device, the method comprising: alternately stacking first material layers and second material layers; forming holes through the first material layers and the second material layers; forming a charge storage layer, a tunnel insulating layer including a multilayered structure, and a channel layer within each of the holes; forming a slit between the holes through the first material layers and the second material layers; removing the second material layers exposed through the slit to form recess regions; forming a blocking insulating layer on a surface of the charge storage layer exposed by removing the second material layer; and forming a conductive pattern on the blocking insulating layer within the recess regions, wherein the forming of the tunnel insulating layer including the multilayered structure comprises: forming a thermal oxide layer on the charge storage layer; and forming a radical oxide layer on the thermal oxide layer, wherein a surface of the thermal oxide layer is in contact with the charge storage layer.

10. The method of claim 9 , wherein the multilayered structure includes the thermal oxide layer and at least one of the radical oxide layer, a dry oxide layer, and a wet oxide layer.

11. The method of claim 9 , wherein forming the radical oxide layer on the thermal oxide layer comprises:
using the thermal oxide layer to prevent a layer from being formed between the charge storage layer and the tunnel insulating layer during the formation of the radical oxide layer.

12. The method of claim 9 , wherein forming the radical oxide layer on the thermal oxide layer comprises:
using the thermal oxide layer to prevent a shallow trap layer from being formed between the charge storage layer and the tunnel insulating layer during the formation of the radical oxide layer.

13. The method of claim 9 , wherein the forming of the radical oxide layer comprises:
forming a nitride layer or a polysilicon (poly-Si) layer on the thermal oxide layer; and
performing a radical oxidation process on the nitride layer or the poly-Si layer.

14. The method of claim 13 , wherein the thermal oxide layer prevents a SiON layer from being formed at an interface between the charge storage layer and the tunnel insulating layer during the radical oxidation process.

15. The method of claim 13 , further comprising:
using the thermal oxide layer to prevent a shallow trap layer from being formed at an interface between the charge storage layer and the tunnel insulating layer during the radical oxidation process.

Assignees

• Sk Hynix Inc

Inventors

• Ko Min Sung

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/685 Primary

  being perpendicular to the channel plane · CPC title