Pixel of a multi-stacked CMOS image sensor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9252178-B2
Application number	US-201113205127-A
Country	US
Kind code	B2
Filing date	Aug 8, 2011
Priority date	Feb 1, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.

First claim

What is claimed is:

1. A pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor, the pixel comprising:
a light-receiving unit comprising: a first subpixel unit, a second subpixel unit located above the first subpixel unit, and a third subpixel unit located above the second subpixel unit, wherein the light receiving unit is substantially rectangular in shape and has a first side and has an adjacent second side;
an integrated circuit (IC) located in the bottom of the pixel, and at least partially located below the light receiving unit;
a first extension electrode unit extending from the first subpixel and extending out of the first side of the light receiving unit;
a second extension electrode unit extending from the second subpixel and extending out of the first side of the light receiving unit;
a third extension electrode unit extending from the third subpixel unit and extending out of the first side of the light receiving unit;
a fourth extension electrode unit extending out of the adjacent second side of the light receiving unit, wherein the fourth extension electrode unit extends orthogonally with respect to the first extension electrode unit;
a first contact plug connecting the first extension electrode unit to a first transistor in the IC;
a second contact plug connecting the second extension electrode to a second transistor in the IC;
a third contact plug connecting the third extension electrode to a third transistor in the IC; and
a fourth contact plug connecting the fourth extension electrode to a common electrode terminal,
wherein the first, second, and third extension electrode units are laterally offset in a plan view.

2. The pixel of claim 1 , wherein each contact plug is partially surrounded by at least one insulating layer.

3. The pixel of claim 1 , wherein each of the subpixel units comprises at least one of an organic semiconductor layer, a crystal silicon layer, an amorphous silicon layer, a copper indium gallium selenide (CIGS) layer, and a quantum dot layer.

4. The pixel of claim 1 , further comprising:
a fifth extension electrode unit extending out of the adjacent second side of the light receiving unit, such that the fifth extension electrode unit extends orthogonally with respect to the first extension electrode unit; and
a sixth extension electrode unit extending out of the adjacent second side of the light receiving unit, such that the sixth extension electrode unit extends orthogonally with respect to the first extension electrode unit.

5. The pixel of claim 1 , further comprising:
a fifth extension electrode unit extending out of the adjacent second side of the light receiving unit, such that the fifth extension electrode unit extends orthogonally with respect to the first extension electrode unit; and
a sixth extension electrode unit extending out of the adjacent second side of the light receiving unit, such that the sixth extension electrode unit extends orthogonally with respect to the first extension electrode unit, and
wherein the first, second, and third extension electrode units extend in parallel with each other out of the first side of the light receiving unit, and
wherein the fourth, fifth, and sixth extension electrode units extend in parallel with each other out of the adjacent second side of the light receiving unit and
wherein the fourth, fifth, and sixth extension electrodes connect to the common electrode terminal through the fourth contact plug, a fifth contact plug, and a sixth contact plug respectively.

6. The pixel of claim 1 , wherein the extension electrode units are located along the perimeter of the light receiving unit.

Assignees

• Park Kyung-Bae
• Kim Kyu-Sik
• Jin Yong-Wan
• Choi Woong
• Lee Kwang-Hee
• Kim Do-Hwan
• Samsung Electronics Co Ltd

Inventors

• Park Kyung-Bae
• Kim Kyu-Sik
• Jin Yong-Wan
• Choi Woong
• Lee Kwang-Hee
• Kim Do-Hwan

Classifications

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10F39/024 Primary

  of coatings or optical elements · CPC title

• H10F39/026

  Wafer-level processing · CPC title

• H10F39/803

  Pixels having integrated switching, control, storage or amplification elements · CPC title