Array substrate and fabrication method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9252159-B2
Application number	US-201314081639-A
Country	US
Kind code	B2
Filing date	Nov 15, 2013
Priority date	Nov 16, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

The present invention discloses an array substrate comprising a plurality of common electrode lines, a plurality of gate lines, and a plurality of data lines formed on a substrate, and a plurality of pixel units formed among the gate lines, the data lines and the common electrode lines, each pixel unit comprises: a pixel electrode, a first TFT, and a common electrode, the gate line and the data line drive the pixel electrode through the first TFT, the common electrode line is connected to the common electrode, the common electrode line and the data line do not overlap with each other, and an insulating layer is disposed between the common electrode line and the date line. The present invention further discloses a fabrication method of the array substrate and a display device comprising the array substrate.

First claim

The invention claimed is:

1. An array substrate, comprising a plurality of common electrode lines, a plurality of gate lines and a plurality of data lines formed on a substrate, and a plurality of pixel units formed among the gate lines, the data lines and the common electrode lines, wherein each pixel unit comprises:
a pixel electrode;
a first TFT; and
a common electrode;
wherein, gate of the first TFT is connected to the gate line, source of the first TFT is connected to the data line, drain of the first TFT is connected to the pixel electrode, and the common electrode line is connected to the common electrode,
wherein, the common electrode line and the data line do not overlap with each other,
wherein the pixel electrode and the common electrode are implemented in different layers and overlapped with each other,
wherein the pixel unit further comprises a second TFT for connecting the common electrode line to the common electrode,
wherein, gate of the second TFT is connected to the gate line, source of the second TFT is connected to the common electrode line, and drain of the second TFT is connected to the common electrode.

2. The array substrate of any of claim 1 , wherein, the common electrode line is parallel to the data line.

3. The array substrate of any of claim 1 , wherein, an insulating layer is disposed between the common electrode line and the gate line, and between the data line and the gate line.

4. The array substrate of any of claim 1 , wherein, the common electrode line and the data line are disposed at a same level.

5. A display device, comprising the array substrate of claim 1 .

6. The display device of claim 5 , wherein, the common electrode line is parallel to the data line.

7. The display device of claim 5 , wherein, an insulating layer is disposed between the common electrode line and the gate line, and between the data line and the gate line.

8. The display device of claim 5 , wherein, the common electrode line and the data line are disposed at a same level.

9. A fabrication method of an array substrate, comprising the following steps:
forming a gate line, a first gate and a gate insulating layer on a substrate, and connecting the first gate to the gate line;
forming a first active layer;
forming a first source, a first drain, a data line and a common electrode line which is not overlapping with the data line, and connecting the first source to the data line; and
forming a common electrode, a pixel electrode and a passivation layer between the common electrode and the pixel electrode, connecting the common electrode to the common electrode line, and connecting the pixel electrode to the first drain,
wherein the pixel electrode and the common electrode are implemented in different layers and overlapped with each other,
wherein, forming the passivation layer on the common electrode, and forming the pixel electrode on the passivation layer,
forming a via passing through the passivation layer and connecting the pixel electrode to the first drain through the via, and
wherein, forming a second gate at the same time as forming the first gate and connecting the second gate to the gate line;
forming a second active layer at the same time as forming the first active layer;
forming a second source and a second drain at the same time as forming the first source, the first drain, the data line and the common electrode line, and connecting the second source to the common electrode line;
forming the common electrode after forming the second source and the second drain, and connecting the common electrode to the second drain.

10. The method of claim 9 , wherein the common electrode line is parallel to the data line.

11. A fabrication method of an array substrate, comprising the following steps:
forming a gate line, a first gate and a gate insulating layer on a substrate, and connecting the first gate to the gate line;
forming a first active layer;
forming a first source, a first drain, a data line and a common electrode line which is not overlapping with the data line, and connecting the first source to the data line; and
forming a common electrode, a pixel electrode and a passivation layer between the common electrode and the pixel electrode, connecting the common electrode to the common electrode line, and connecting the pixel electrode to the first drain,
wherein the pixel electrode and the common electrode are implemented in different layers and overlapped with each other,
wherein, forming the passivation layer on the pixel electrode, and forming the common electrode on the passivation layer, and
wherein, forming a second gate at the same time as forming the first gate and connecting the second gate to the gate line;
forming a second active layer at the same time as forming the first active layer;
forming a second source and a second drain at the same time as forming the first source, the first drain, the data line and the common electrode line, and connecting the second source to the common electrode line;
forming a via after forming the passivation layer, and connecting the common electrode to the second drain through the via.

12. The method of claim 11 , wherein the common electrode line is parallel to the data line.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Liu Jiarong
• Yao Zhixiao
• Lin Hongtao

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F2001/134372

  Physics · mapped topic

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title