Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Package stacked device
US9252136B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9252136-B2 |
| Application number | US-201414468885-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 26, 2014 |
| Priority date | Apr 7, 2014 |
| Publication date | Feb 2, 2016 |
| Grant date | Feb 2, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A package stacked device may include a first packaging body layer having a first chip embedded therein, and a second packaging body layer positioned under the first packaging body layer and having a second chip embedded therein. The package stacked device may also include a first connection unit protruding from a first bottom surface of the first packaging body layer, a second connection unit protruding from a second top surface of the second packaging body layer, a first covering layer providing a first opening to expose the top surface of the second connection unit and substantially covering the second top surface of the second packaging body layer, and a first adhesive layer substantially covering the exposed top surface of the second connection unit within the first opening. The first connection unit may be inserted into the first opening and connected to the first adhesive layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A package stacked device comprising: a first packaging body layer having a first chip embedded therein; a second packaging body layer positioned under the first packaging body layer and having a second chip embedded therein; a first connection unit protruding from a first bottom surface of the first packaging body layer; a second connection unit protruding from a second top surface of the second packaging body layer; a first covering layer providing…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9252136B2 cover?
- A package stacked device may include a first packaging body layer having a first chip embedded therein, and a second packaging body layer positioned under the first packaging body layer and having a second chip embedded therein. The package stacked device may also include a first connection unit protruding from a first bottom surface of the first packaging body layer, a second connection unit p…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).