Semiconductor device and manufacturing method thereof
US-8994159-B2 · Mar 31, 2015 · US
Resin package
US9252090B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9252090-B2 |
| Application number | US-201313980336-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2013 |
| Priority date | Mar 28, 2012 |
| Publication date | Feb 2, 2016 |
| Grant date | Feb 2, 2016 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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Abstract
Official abstract text for this publication.
A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate.
First claim
Opening claim text (preview).
The invention claimed is: 1. A resin package comprising: a die pad having a main surface on which a chip is mounted; at least one lead terminal electrically connected to the chip; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and sealing resin which covers the chip and the thin plate; wherein one surface of the thin plate is roughened, one of the main surface of the die pad and the main surface of the thin plate has a first fixing hole, the other of the main surface of the die pad and the main surface of the thin plate has a first fixing projection, and the first fixing hole and the first fixing projection are engaged with each other. 2. The resin package according to claim 1 , wherein the thin plate is positioned around the chip on the main surface of the die pad. 3. The resin package according to claim 1 , wherein a plurality of the thin plates are positioned at opposite sides of a region where the chip is mounted on the main surface of the die pad. 4. The resin package according to claim 1 , wherein the first fixing hole and the first fixing projection are crimped. 5. The resin package according to claim 1 , wherein one of the main surface of the at least one lead terminal and a main surface of the thin plate has a second fixing hole, the other of the main surface of the at least one lead terminal and the main surface of the thin plate has a second fixing projection, and the second fixing hole and the second fixing projection are engaged with each other. 6. The resin package according to claim 5 , wherein the second fixing hole and the second fixing projection are crimped. 7. The resin package according to claim 1 , wherein both surfaces of the thin plate are roughened. 8. The resin package according to claim 1 , wherein the surface of the thin plate is roughened in advance, before the thin plate is attached to the die pad. 9. The resin package according to claim 1 , wherein the thin plate is roughened by forming at least one of grooves or holes.
Assignees
Inventors
Classifications
between laterally-adjacent chips · CPC title
the semiconductor body being completely enclosed · CPC title
Encapsulations, e.g. protective coatings · CPC title
being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title
the connected ends being ball-shaped · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9252090B2 cover?
- A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin …
- Who is the assignee on this patent?
- Panasonic Corp, Panasonic Ip Man Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W70/461. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).