Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9252031-B2
Application number	US-201414493379-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Sep 23, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower heat-transfer layer disposed on the lower semiconductor chip;
an interposer provided on the lower package, the interposer comprising an interposer substrate, a first heat-transfer opening defined by a recessed bottom surface of the interposer substrate, a second heat-transfer opening defined by a recessed top surface of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad; and
an upper package provided on the interposer, the upper package comprising an upper package substrate, an upper package heat-transfer pad disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate,
wherein the lower heat-transfer layer is provided in the first heat-transfer opening to be in contact with the upper interposer heat-transfer pad exposed to the first heat-transfer opening, and the upper heat-transfer layer is provided in the third heat-transfer opening to contact the upper package heat-transfer pad.

2. The semiconductor package of claim 1 , further comprising a lower interposer heat-transfer pad provided spaced apart from the upper interposer heat-transfer pad and disposed in the first heat-transfer opening,
wherein the lower interposer heat-transfer pad contacts the lower heat-transfer layer.

3. The semiconductor package of claim 2 , wherein:
the interposer substrate includes internal wires and the lower interposer heat-transfer pad includes a portion of internal wires of the interposer substrate; and
the lower heat-transfer layer is formed of a thermal interface material.

4. The semiconductor package of claim 1 , further comprising conductive connecting portions interposed between the lower package and the interposer to connect the lower package electrically to the interposer.

5. The semiconductor package of claim 4 , further comprising an under-fill resin layer filling a gap region between the lower package and the interposer and contacting the conductive connecting portions.

6. The semiconductor package of claim 4 , further comprising a lower molding layer provided on the lower package substrate to cover the lower semiconductor chip,
wherein the lower molding layer is provided to define through-holes, in which the conductive connecting portions, respectively, are disposed.

7. The semiconductor package of claim 1 , wherein the interposer substrate is a printed circuit board including a plurality of insulating layers and internal wires provided between the insulating layers.

8. The semiconductor package of claim 7 , wherein the upper interposer heat-transfer pad includes a portion of the internal wires.

9. The semiconductor package of claim 1 , wherein the lower heat-transfer layer has a thickness that is equal to or larger than a depth of the first heat-transfer opening.

10. The semiconductor package of claim 1 , wherein the upper heat-transfer layer has a thickness that is equal to or larger than a sum of depths of the second and third heat-transfer openings.

11. The semiconductor package of claim 1 , further comprising upper solder balls provided on the bottom surface of the upper package substrate that electrically contact the top surface of the interposer substrate.

12. A semiconductor package, comprising:
a lower package including a lower package substrate and at least a first semiconductor chip disposed thereon;
an interposer stacked on the lower package, the interposer:
including internal wires and a plurality of insulating layers,
having an upper surface and a lower surface, and
including an upper recess at the upper surface and a lower recess, opposite the upper recess, at the lower surface;

an upper package including an upper package substrate and at least a second semiconductor chip disposed thereon; and
a lower heat transfer layer formed of a thermal interface material, the lower heat transfer layer disposed in the lower recess and thermally connecting the first semiconductor chip to at least a first internal wire of the interposer.

13. The semiconductor package of claim 12 , further comprising:
an upper heat transfer layer, the upper heat transfer layer disposed in the upper recess and thermally connecting the upper package substrate to at least a second internal wire of the interposer.

14. The semiconductor package of claim 13 , wherein:
at least the lower heat transfer layer, the first internal wire, the second internal wire, and the upper heat transfer layer are thermally connected to form a heat transfer path positioned to transfer heat from the first semiconductor chip to the upper package substrate.

15. The semiconductor package of claim 14 , wherein:
the upper package includes at least a third internal wire thermally connected to the upper heat transfer layer.

16. The semiconductor package of claim 15 , wherein:
the lower heat transfer layer contacts the first semiconductor chip and contacts the first internal wire; and
the upper heat transfer layer contacts the second internal wire and contacts the third internal wire.

17. The semiconductor package of claim 13 , wherein:
the upper heat transfer layer is formed of a thermal interface material.

18. The semiconductor package of claim 12 , wherein:
the lower heat transfer layer contacts the first semiconductor chip and contacts the first internal wire.

19. A method of fabricating a semiconductor package, comprising:
forming lower conductive connecting portions on a lower package substrate;
mounting a lower semiconductor chip on the lower package substrate provided with the lower conductive connecting portions;
forming a lower heat-transfer layer on the lower semiconductor chip;
stacking an interposer, including an interposer substrate and upper conductive connecting portions attached to a bottom surface of the interposer substrate, on the lower semiconductor chip, in such a way that the upper conductive connecting portions are attached to the lower conductive connecting portions;
performing a reflow process to the lower and upper conductive connecting portions to form conductive connecting portions;
forming an under-fill resin layer between the lower package substrate and the interposer substrate; and
stacking an upper package on the interposer.

20. The method of claim 19 , further comprising, before the stacking of the interposer,
etching a portion of a bottom surface of the interposer substrate to form a first heat-transfer opening exposing a lower interposer heat-transfer pad; and
etching a portion of a top surface of the interposer substrate to form a second heat-transfer opening exposing an upper interposer heat-transfer pad.

21. The method of claim 20 , wherein the stacking of the interposer comprises providing the lower heat-transfer layer in the first heat-transfer opening to be in contact with the lower interposer heat-transfer pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Im Hohyeuk
• Kim Jongkook
• Seong Gowoon
• Lee Seokwon
• Jang Byoungwook
• Cho Eunseok

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title