Ultra-shallow junction semiconductor field-effect transistor and method of making

Patent metadata

Field	Value
Publication number	US-9252015-B2
Application number	US-201213704598-A
Country	US
Kind code	B2
Filing date	Dec 12, 2012
Priority date	Dec 12, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a target. The PVD process is followed by annealing, during which ultra-shallow junctions and ultra-thin metal silicide are formed. After removing the mixture film remaining on the semiconductor substrate, an ultra-shallow junction semiconductor field-effect transistor is formed. Because the mixture film comprises metal and semiconductor dopants, ultra-shallow junctions and ultra-thin metal silicide can be formed in a same annealing process. The ultra-shallow junction thus formed can be used in semiconductor field-effect transistors for the 14 nm, 11 nm, or even further technology node.

First claim

We claim:

1. A method of making an ultra-shallow junction semiconductor field-effect transistor, comprising:
A. forming a gate structure on a semiconductor substrate;
B. using the gate structure as a mask, and using a metal and semiconductor dopant mixture as a target, depositing a film of the mixture on the semiconductor substrate by physical vapor deposition;
C. performing annealing on the semiconductor substrate with the film of the mixture deposited thereon, to form metal silicide and ultra-shallow junctions, the ultra-shallow junction being a PN junction or a metal-semiconductor junction; and
D. removing the film of the mixture remaining on a surface of the semiconductor substrate.

2. The method of claim 1 , wherein a conventional rapid thermal annealing (RIP) process or a microwave heating annealing is used in Step C.

3. The method of claim 2 , wherein during microwave annealing, multi-mode and multi-frequency microwaves are provided in a microwave-heating chamber to heat up both metal and semiconductor dopants in the film of the mixture.

4. The method of claim 3 , wherein during microwave annealing, microwave frequencies are between 1.5 GHz and 15 GHz, and the microwave annealing lasts about 1 minute to about 30 minutes.

5. The method of claim 1 , wherein in step B, a target material is ionized into an ionic state, causing it to produce metal ions and semiconductor dopant ions, and wherein a substrate bias voltage is applied to the semiconductor substrate.

6. The method of claim 5 , a first bias voltage is applied to the target to ionize the target material into an ionic state.

7. The method of claim 6 , wherein the first bias voltage is one of a direct current bias voltage, an alternating current bias voltage and a pulsed bias voltage.

8. The method of claim 5 , wherein the substrate bias voltage is one of a direct current bias voltage, an alternating current bias voltage and a pulsed bias voltage.

9. The method according to claim 1 , wherein the metal is any of nickel (Ni), platinum (Pt), titanium (Ti), cobalt (Co), tungsten (W) and Molybdenum (Mo) or a mixture or alloy of two or more thereof.

10. The method according to claim 1 , wherein the semiconductor dopant can be one or more P-type dopants such as boron (B), boron fluoride (BF 2 ), indium (Indium) or any mixture thereof; or one or more N-type dopants such as phosphorus (P), arsenic (As) or any mixture thereof.

11. The method according to claim 1 , wherein a semiconductor dopant content in the mixture of metal and semiconductor dopants is about 0.1 percent to about 5 percent.

12. The method according to claim 1 , wherein the semiconductor substrate includes silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), and/or any of the III-V semiconductors.

13. The method according to claim 1 , wherein the semiconductor substrate is at a temperature between 0 and 300° C. during deposition of the mixture film on the semiconductor substrate in step B.

14. The method according to claim 1 , wherein an annealing temperature is between 300 to 800° C. in step C.

Assignees

• Univ Fudan

Inventors

• Wu Dongping
• Zhou Xiangbiao
• Xu Peng
• Zhang Wei
• Zhang Shi-Li

Classifications

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/14 Primary

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10D30/0223

  having source and drain regions or source and drain extensions self-aligned to sides of the gate · CPC title

• H10D30/0212

  using self-aligned silicidation · CPC title