System supporting multiple partitions with differing translation formats

US9251089B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9251089-B2
Application numberUS-201313784082-A
CountryUS
Kind codeB2
Filing dateMar 4, 2013
Priority dateOct 8, 2012
Publication dateFeb 2, 2016
Grant dateFeb 2, 2016

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  1. Title

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  2. Abstract

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Abstract

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A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of facilitating memory access, said method comprising: providing a first partition within a system configuration, the first partition configured to support an operating system (OS) designed for a first address translation architecture, wherein configuration of the first partition to support the OS designed for the first address translation architecture is indicated in a configuration data structure, and wherein the first partition is not configured, as indicated in the configuration data structure, to support an OS designed for a second address translation architecture; and providing a second partition within the system configuration, the second partition configured to support the OS designed for the second address translation architecture, the second partition not configured to support the OS designed for the first address translation architecture, wherein the first address translation architecture is structurally different from the second address translation architecture, and wherein the first partition is a paravirtualized partition in which a guest of the first partition assists in handling address translation faults corresponding to host translations, and the second partition is a virtualized partition in which handling of address translation faults corresponding to host translations is independent of assistance from a guest of the second partition. 2. The method of claim 1 , wherein the first address translation architecture uses a hash structure and the second address translation architecture uses a hierarchical table structure. 3. The method of claim 1 , wherein the first partition uses a single level address translation mechanism for translating guest virtual addresses to host physical addresses, and the second partition uses a nested level address translation mechanism for translating guest virtual addresses to host physical addresses. 4. The method of claim 3 , wherein the nested level address translation mechanism includes a first translation structure to translate a guest virtual address to a guest physical address and a second translation structure to translate the guest physical address to a host physical address. 5. The method of claim 4 , wherein the first translation structure comprises one of a hierarchical structure, a hash structure or an offset structure, and the second translation structure comprises one of a hierarchical structure, a hash structure or an offset structure. 6. The method of claim 1 , wherein the first partition and the second partition are supported by a single hypervisor. 7. The method of claim 1 , further comprising sharing memory by the first partition and the second partition, wherein the memory is shared by the first partition and the second partition which use structurally different address translation architectures. 8. The method of claim 7 , further comprising managing by a hypervisor supporting the first partition and the second partition the memory that is shared, wherein the managing includes at least one of: removing a page from the memory, storing a page of the memory in another form of memory, paging out a page of the memory, or compressing a page of the memory. 9. The method of claim 1 , further comprising cloning one of the first partition and the second partition to provide memory to be shared by multiple partitions using structurally different address translation architectures. 10. The method of claim 1 , further comprising: identifying a page of memory that is the same in the first partition and the second partition; and removing the page from one of the first partition and the second partition, wherein the page that remains is shared by the first partition and the second partition. 11. The method of claim 1 , wherein the configuration data structure indicates at least one of a type of address translation structure to be used for host level translations or an indication of whether the first partition is to use a single level translation or a nested level translation.

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Classifications

  • for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

  • involving hashing techniques, e.g. inverted page tables · CPC title

  • Performance improvement · CPC title

  • using page tables, e.g. page table structures · CPC title

  • Management of space entities, e.g. partitions, extents, pools · CPC title

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What does patent US9251089B2 cover?
A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F12/1018. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).