Nonvolatile cache memory, processing method of nonvolatile cache memory, and computer system

Patent metadata

Field	Value
Publication number	US-9251057-B2
Application number	US-201213681999-A
Country	US
Kind code	B2
Filing date	Nov 20, 2012
Priority date	Nov 29, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Disclosed is a nonvolatile cache memory including a nonvolatile memory part and a cache controller. The nonvolatile memory part is configured to store cache data. The cache controller is configured to control reading and writing of the cache data with respect to the nonvolatile memory part. Further, the cache controller is configured to perform, as a preparation for an interruption of power supply, standby preparation processing to generate standby state data and store the generated standby state data in the nonvolatile memory part. Further, the cache controller is configured to perform, at resumption of the power supply, restoration processing of the cache data stored in the nonvolatile memory part using the standby state data.

First claim

What is claimed is:

1. A nonvolatile cache memory, comprising:
a nonvolatile memory part having a plurality of cache lines configured to store cache data; and
a cache controller configured to:
control reading and writing of the cache data with respect to the nonvolatile memory part,
perform standby preparation processing to generate standby state data by converting the plurality of cache lines in the nonvolatile memory part into data structures for use in a standby state and storing the generated standby state data in the nonvolatile memory part, and
perform restoration processing of the cache data stored in the nonvolatile memory part, effective upon resumption of the power supply, said restoration processing including reconverting the plurality of cache lines into data structures for an operation state.

2. The nonvolatile cache memory according to claim 1 , wherein
the cache controller is configured to:
generate the standby state data containing error correcting data enabling error correction of at least the cache data stored in the nonvolatile memory part and store the generated standby state data in the nonvolatile memory part as the standby preparation processing, and
perform error correction processing of the cache data stored in the nonvolatile memory part using the error correcting data contained in the standby state data as the restoration processing.

3. The nonvolatile cache memory according to claim 1 , wherein
the nonvolatile memory part has a plurality of cache lines each containing a cache data area and a standby state data area, and
the cache controller is configured to perform, as the standby preparation processing, processing to:
generate for at least part of the cache lines the standby state data containing error correcting data enabling error correction of the cache data stored in the cache line,
store the generated standby state data in the standby state data area, and
bring the cache line into a state representing that the cache line stores the standby state data.

4. The nonvolatile cache memory according to claim 1 , wherein
the cache controller is configured to:
generate the standby state data containing error detecting data enabling error detection of at least the cache data stored in the nonvolatile memory part and store the generated standby state data in the nonvolatile memory part as the standby preparation processing, and
perform error detection processing of the cache data stored in the nonvolatile memory part using the error detecting data contained in the standby state data as the restoration processing.

5. The nonvolatile cache memory according to claim 4 , wherein the cache controller is configured to perform processing to invalidate the cache data from which an error is detected by the error detection processing.

6. The nonvolatile cache memory according to claim 1 , wherein
the cache controller is configured to perform standby preparation processing when a number of invalid cache lines is greater than a number of necessary cache lines.

7. A nonvolatile cache memory, comprising:
a nonvolatile memory part having a plurality of cache lines configured to store cache data;
a cache controller configured to:
control reading and writing of the cache data with respect to the nonvolatile memory part,
perform, as a preparation for an interruption of power supply, standby preparation processing to generate standby state data and store the generated standby state data in the nonvolatile memory part,
perform, at resumption of the power supply, restoration processing of the cache data stored in the nonvolatile memory part using the standby state data,
generate for at least part of the cache lines the standby state data containing error correcting data enabling error correction of the cache data stored in the cache line,
store the generated standby state data in another of the cache lines, and
bring the other cache line into a state representing that the cache line stores the standby state data.

8. The nonvolatile cache memory according to claim 7 , wherein the standby state data containing the error correcting data further contains address information of the cache line storing the cache data on which the error correction is performed using the error correcting data.

9. The nonvolatile cache memory according to claim 7 , wherein the cache controller is configured to store the standby state data in an area corresponding to the cache line storing the cache data as an object of the standby state data.

10. The nonvolatile cache memory according to claim 1 , wherein the cache controller is configured to perform the standby preparation processing upon receiving a standby signal requesting for shifting to a standby state where the power supply is interrupted.

11. A processing method of a nonvolatile cache memory having a nonvolatile memory part containing a plurality of cache lines configured to store cache data, the processing method comprising:
performing standby preparation processing to generate standby state data by converting the plurality of cache lines in the nonvolatile memory part into data structures for use in a standby state and storing the generated standby state data in the nonvolatile memory part, and
performing restoration processing of the cache data stored in the nonvolatile memory part, during resumption of the power supply and reconverting the plurality of cache lines into data structures for an operation state.

12. The processing method according to claim 11 , further comprising:
generating the standby state data containing error correcting data enabling error correction of at least the cache data stored in the nonvolatile memory part and store the generated standby state data in the nonvolatile memory part as the standby preparation processing, and
performing error correction processing of the cache data stored in the nonvolatile memory part using the error correcting data contained in the standby state data as the restoration processing.

13. The processing method according to claim 11 , further comprising:
generating for at least part of the cache lines the standby state data containing error correcting data enabling error correction of the cache data stored in the cache line,
storing the generated standby state data in the standby state data area, and
bringing the cache line into a state representing that the cache line stores the standby state data.

14. The processing method according to claim 13 , wherein the cache controller is configured to perform processing to invalidate the cache data from which an error is detected by the error detection processing.

15. The processing method according to claim 11 , further comprising:
generating the standby state data containing error detecting data enabling error detection of at least the cache data stored in the nonvolatile memory part and store the generated standby state data in the nonvolatile memory part as the standby preparation processing, and
performing error detection processing of the cache data stored in the nonvolatile memory part using the error detecting data contained in the standby state data as the restoration processing.

16. A computer system, comprising:
a processor;
a nonvolatile cache memory;
a power control circuit; and
a main memory,
the power control circuit being configured to control power supply to the processor and the nonvolatile cache memory,
the processor being configured to:
perform reading and writing of data with respect to the main memory via the nonvolatile cache memory,
transmit a standby signal requesting for shifti

Assignees

• Sony Corp

Inventors

• Higo Yutaka
• Hosomi Masanori
• Ohmori Hiroyuki
• Bessho Kazuhiro
• Asayama Tetsuya
• Yamane Kazutaka
• Uchida Hiroyuki

Classifications

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• G06F2212/222

  Non-volatile memory · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06F11/1666

  where the redundant component is memory or memory area · CPC title