Channel rotating error correction code

Patent metadata

Field	Value
Publication number	US-9251001-B2
Application number	US-201514740449-A
Country	US
Kind code	B2
Filing date	Jun 16, 2015
Priority date	Sep 6, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

First claim

What is claimed is:

1. A method for writing data to a multiple channel memory module, comprising:
setting a start value of n for 0≦n≦m for the multi-channel memory module comprising m channels where n and m are integers greater than or equal to zero and m is at least 1 greater than n;
until the writing of the data is complete:
writing data DATn to a channel CHn of the memory module;
if n=m−1, simultaneously writing in parallel an error correction code ECCn corresponding to the data DATn to another channel CH(start) of the memory module and then resetting n to a value different from the start value;
otherwise, if n≠m−1, simultaneously writing in parallel an error correction code ECCn corresponding to the data DATn to another channel CH(n+1) of the memory module and then incrementing n.

2. The method of claim 1 , wherein setting the start value comprises:
setting the start value to a different channel of the memory module than one or more previously-set start values.

3. The method of claim 1 , wherein setting the start value comprises:
setting the start value based on one or more of:
a bandwidth usage for each of the channels;
a distribution of one or more previous writes among the channels; and
an arrangement of data previously stored in the memory module.

4. A method for reading data from a multiple channel memory module, the method comprising:
setting a start value of n for 0≦n≦m for the multi-channel memory module comprising m channels where n and m are integers greater than or equal to zero and m is at least 1 greater than n;
until a reading of data is complete:
reading data DATn from a channel CHn of the memory module;
if n=m−1, simultaneously reading in parallel an error correction code ECCn corresponding to the data DATn from another channel CH(start) of the memory module and then resetting n to a value different from the start value;
otherwise, if n≠m−1, simultaneously reading in parallel an error correction code ECCn corresponding to the data DATn from another channel CH(n+1) of the memory module and then incrementing n.

5. The method of claim 4 , wherein setting the start value comprises:
setting the start value to a different channel of the memory module than one or more previously-set start values.

6. The method of claim 4 , wherein setting the start value comprises:
setting the start value based on one or more of:
a bandwidth usage for each of the channels;
a distribution of one or more previous reads among the channels; and
an arrangement of data previously stored in the memory module.

7. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for writing data to a multiple channel memory module, the method comprising:
setting a start value of n for 0≦n≦m for the multi-channel memory module comprising m channels where n and m are integers greater than or equal to zero and m is at least 1 greater than n;
until the writing of the data is complete:
writing data DATn to a channel CHn of the memory module;
if n=m−1, simultaneously writing in parallel an error correction code ECCn corresponding to the data DATn to another channel CH(start) of the memory module and then resetting n to a value different from the start value;
otherwise, if n≠m−1, simultaneously writing in parallel an error correction code ECCn corresponding to the data DATn to another channel CH(n+1) of the memory module and then incrementing n.

8. The non-transitory computer-readable storage medium of claim 7 , wherein setting the start value comprises:
setting the start value to a different channel of the memory module than one or more previously-set start values.

9. The non-transitory computer-readable storage medium of claim 7 , wherein setting the start value comprises:
setting the start value based on one or more of:
a bandwidth usage for each of the channels;
a distribution of one or more previous writes among the channels; and
an arrangement of data previously stored in the memory module.

10. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for reading data from a multiple channel memory module, the method comprising:
setting a start value of n for 0≦n≦m for the multi-channel memory module comprising m channels where n and m are integers greater than or equal to zero and m is at least 1 greater than n;
until the reading of the data is complete:
reading data DATn from a channel CHn of the memory module;
if n=m−1, simultaneously reading in parallel an error correction code ECCn corresponding to the data DATn from another channel CH(start) of the memory module and then resetting n to a value different from the start value;
otherwise, if n≠m−1, simultaneously reading in parallel an error correction code ECCn corresponding to the data DATn from another channel CH(n+1) of the memory module and then incrementing n.

11. The non-transitory computer-readable storage medium of claim 10 , wherein setting the start value comprises:
setting the start value to a different channel of the memory module than one or more previously-set start values.

12. The non-transitory computer-readable storage medium of claim 10 , wherein setting the start value comprises:
setting the start value based on one or more of:
a bandwidth usage for each of the channels;
a distribution of one or more previous reads among the channels; and
an arrangement of data previously stored in the memory module.

13. A computing device, comprising:
a processor;
a multi-channel memory module comprising m channels;
the multi-channel memory module:
setting a start value of n for 0≦n≦m for the multi-channel memory module where n and m are integers greater than or equal to zero and m is at least 1 greater than n;
until a writing of data is complete:
writing data DATn to a channel CHn of the memory module;
if n=m−1, simultaneously writing in parallel an error correction code ECCn corresponding to the data DATn to another channel CH(start) of the memory module and then resetting n to a value different from the start value;
otherwise, if n≠m−1, simultaneously writing in parallel an error correction code ECCn corresponding to the data DATn to another channel CH(n+1) of the memory module and then incrementing n.

14. The computing device of claim 13 , wherein the memory module is a through silicon via dynamic random access memory module.

15. The computing device of claim 13 , wherein setting the start value comprises:
setting the start value to a different channel of the memory module than one or more previously-set start values.

16. The computing device of claim 13 , wherein setting the start value comprises:
setting the start value based on one or more of:
a bandwidth usage for each of the channels;
a distribution of one or more previous writes among the channels; and
an arrangement of data previously stored in the memory module.

17. A computing device, comprising:
a processor;
a multi-channel memory module comprising m channels;
the multi-channel memory module:
setting a start value of n for 0≦n≦m for the multi-channel memory module where n and m are integers greater than or equal to zero and m is at least 1 greater than n;
until a reading of data is complete:
reading data DATn from a channel CHn of the memory module;
if n=m−1, simultaneously reading in parallel an error correction code ECCn corresponding to the data DATn from another channel CH(start) of the memory mo

Assignees

• Osborn Michael J
• Hummel Mark D
• Mayhew David E
• Advanced Micro Devices Inc

Inventors

• Osborn Michael J
• Hummel Mark D
• Mayhew David E

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title