Memory compatibility system and method

Patent metadata

Field	Value
Publication number	US-9250934-B2
Application number	US-201414149339-A
Country	US
Kind code	B2
Filing date	Jan 7, 2014
Priority date	Aug 31, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

First claim

What is claimed is:

1. A memory system, comprising:
a first connector that is configured to connect to a processing system through a first socket, wherein the first connector and first socket conform to a first Dynamic Random Access Memory (DRAM) interface standard;
a second socket that is configured to connected to a memory module, wherein the second socket and the memory module conform to a second DRAM interface standard;
a virtualization module that is communicatively coupled to the first connector and the second socket, wherein the virtualization module is configured to present a virtual memory module that conforms to the first DRAM interface standard to the processing system when the first connector is connected to the first socket;
a power regulator that is coupled to the second socket and that is configured to couple to a power source through the first connector, wherein the power regulator is configured to receive a power requirement for the memory module that is determined by the virtualization module when the memory module is connected to the second socket and, in response, regulate power received from the power source through the first connector to provide a regulated power to the second socket that conforms with the power requirement; and
a memory buffer module that is communicatively coupled to the first connector and the second socket, wherein the memory buffer module is configured to receive signals through the first connector that are directed to the virtual memory module, forwarded by the virtualization module to the memory buffer module, and associated with the first DRAM interface standard, perform a translation function on the received signals associated with the first DRAM interface standard to produce translated signals associated with the second DRAM interface standard, and output the translated signals associated with the second DRAM interface standard through the second socket.

2. The memory system of claim 1 , wherein the translation function includes a protocol translation function.

3. The memory system of claim 2 , wherein the protocol translation function includes at least one of an address signal translation function and a command signal translation function.

4. The memory system of claim 1 , wherein the translation function includes an architecture translation function.

5. The memory system of claim 4 , wherein the architecture translation function includes at least one of a bank translation function, a refresh translation function, and a data rate translation function.

6. The memory system of claim 1 , wherein the translation function includes a Reliability-Availability-Serviceability (RAS) translation function.

7. The memory system of claim 6 , wherein the RAS translation function includes at least one of Cyclic Redundancy Check (CRC) translation function and a parity detection translation function.

8. The memory system of claim 1 , wherein the memory buffer module is configured to initialize the memory module when the memory module is connected to the second socket.

9. The memory system of claim 1 , wherein the first DRAM interface standard is a double data rate fourth generation (DDR4) standard and the second DRAM interface standard is a double data rate third generation (DDR3) standard.

10. An information handling system, comprising:
a processing system;
a first socket that is coupled to the processing system and that conforms to a first DRAM interface standard;
a memory system that is coupled to the processing system through the first socket, the memory system including:
a first connector that is connected to the processing system through the first socket, wherein the first connector conforms to the first DRAM interface standard;
a second socket that that conforms to a second DRAM interface standard that was promulgated earlier in time than the first DRAM interface standard;
a memory module that is connected to the second socket and that conforms to the second DRAM interface standard;
a virtualization module that is communicatively coupled to the first connector and the second socket wherein the virtualization module is configured to present a virtual memory module that conforms to the first DRAM interface standard to the processing system;
a power regulator that is coupled to the second socket, wherein the power regulator is configured to receive a power requirement for the memory module that is determined by the virtualization module and, in response, regulate power from a power source that is connected to the first connector to provide a regulated power to the second socket that conforms with the power requirement; and
a memory buffer module that is communicatively coupled to the first connector and the second socket, wherein the memory buffer module is configured to receive signals from the processing system through the first connector that are directed to the virtual memory module, forwarded by the virtualization module to the memory buffer module, and associated with the first DRAM interface standard, perform a translation function on the received signals associated with the first DRAM interface standard to produce translated signals associated with the second DRAM interface standard, and output the translated signals associated with the second DRAM interface standard through the second socket to the memory module.

11. The IHS of claim 10 , wherein the translation function includes a protocol translation function that includes at least one of an address signal translation function and a command signal translation function.

12. The IHS of claim 10 , wherein the translation function includes an architecture translation function that includes at least one of a bank translation function, a refresh translation function, and a data rate translation function.

13. The IHS of claim 10 , wherein the translation function includes a Reliability-Availability-Serviceability (RAS) translation function that includes at least one of Cyclic Redundancy Check (CRC) translation function and a parity detection translation function.

14. The IHS of claim 10 , wherein the first DRAM interface standard is a double data rate fourth generation (DDR4) standard and the second DRAM interface standard is a double data rate third generation (DDR3) standard.

15. A method, comprising:
providing a memory system including a first connector that conforms to a first DRAM interface standard, a second socket that conforms to a second DRAM interface standard, a power regulator that is coupled to the second socket, a virtualization module that is communicatively coupled to the first connector and the second socket, and a memory buffer module that is communicatively coupled to the first connector and the second socket;
receiving signals, using the virtualization modulo, that are directed to a virtual memory module that is provided by the virtualization module and that conforms to the first DRAM interface standard, wherein the signals are received from a processing system through the first connector when the first connector is connected to a first socket that conforms to the first DRAM interface standard and that is coupled to the processing system;
forwarding, using the virtualization module, the signals to the memory buffer module;
translating, using the memory buffer module, the received signals associated with the first DRAM interface standard to produce translated signals associated with the second DRAM interface standard;
outputting, using the memory buffer module, the translated signals associated with the second DRAM interface standard through the second socket to a memory module that conforms to the se

Assignees

• Dell Products Lp

Inventors

• Berke Stuart
• Sauber William

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G06F9/44557 Primary

  Code layout in executable memory · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title