System, method, and computer program product for calculating settings for a device, utilizing one or more constraints

Patent metadata

Field	Value
Publication number	US-9250931-B2
Application number	US-201213543212-A
Country	US
Kind code	B2
Filing date	Jul 6, 2012
Priority date	Jul 6, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A system, method, and computer program product are provided for calculating settings for a device, utilizing one or more constraints. In use, a plurality of parameters associated with a device is identified. Additionally, one or more constraints are determined, utilizing the plurality of parameters. Further, one or more settings are calculated for the device, utilizing the one or more constraints and the plurality of parameters.

First claim

What is claimed is:

1. A method, comprising:
identifying a plurality of parameters associated with a device, including descriptions of hardware and software installed within the device;
creating a directed acyclic graph (DAG) including a plurality of nodes, where each of the nodes represents a unique variation of the plurality of parameters associated with the device and where at least one node of the DAG is directly pointed to by two or more additional nodes of the DAG,
determining, for each of the plurality of nodes, a speed associated with the node, where the speed is determined based on the parameters represented by the node, and
directing the plurality of nodes within the DAG based on the speed associated with each node; and
calculating one or more settings for the device, utilizing the plurality of nodes included within the DAG.

2. The method of claim 1 , wherein determining the one or more constraints includes identifying a node in the DAG that corresponds to the identified plurality of parameters associated with the device.

3. The method of claim 2 , wherein determining the one or more constraints includes determining a first subset of nodes in the DAG that are definitively slower than or equal in overall speed and performance to the identified node.

4. The method of claim 3 , wherein determining the one or more constraints includes calculating a maximum output that is possible to be produced by the first subset of nodes.

5. The method of claim 4 , wherein the maximum output for the first subset of nodes includes a highest image quality able to be processed and output by the nodes within the first subset for a particular condition.

6. The method of claim 4 , wherein one or more settings are associated with the maximum output that is possible to be produced by the first subset of nodes.

7. The method of claim 4 , wherein the one or more constraints include one or more predetermined settings associated with the maximum output for the first subset of nodes, which are designated as minimum possible settings when calculating the one or more settings for the device.

8. The method of claim 2 , wherein determining the one or more constraints includes determining a second subset of nodes in the DAG that are definitively faster than or equal in overall speed and performance to the identified node.

9. The method of claim 8 , wherein determining the one or more constraints includes calculating a minimum output that is not possible to be produced by the second subset of nodes.

10. The method of claim 9 , wherein the minimum output for the second subset of nodes includes a lowest image quality that is unable to be processed and output by the nodes within the second subset for a particular condition.

11. The method of claim 9 , wherein one or more settings are associated with the minimum output that is not possible to be produced by the second subset of nodes.

12. The method of claim 9 , wherein the one or more constraints include one or more predetermined settings associated with the minimum output for the second subset of nodes, which are designated as maximum possible settings when calculating the one or more settings for the device.

13. The method of claim 1 , wherein the one or more settings calculated for the device include predefined settings for one or more of the plurality of parameters associated with the device.

14. A computer program product embodied on a non-transitory computer readable medium, comprising code for:
identifying a plurality of parameters associated with a device, including descriptions of hardware and software installed within the device;
creating a directed acyclic graph (DAG) including a plurality of nodes, where each of the nodes represents a unique variation of the plurality of parameters associated with the device and where at least one node of the DAG is directly pointed to by two or more additional nodes of the DAG,
determining, for each of the plurality of nodes, a speed associated with the node, where the speed is determined based on the parameters represented by the node, and
directing the plurality of nodes within the DAG based on the speed associated with each node; and
calculating one or more settings for the device, utilizing the plurality of nodes included within the DAG.

15. A system, comprising:
a processor for:
identifying a plurality of parameters associated with a device, including descriptions of hardware and software installed within the device;
creating a directed acyclic graph (DAG) including a plurality of nodes, where each of the nodes represents a unique variation of the plurality of parameters associated with the device and where at least one node of the DAG is directly pointed to by two or more additional nodes of the DAG,
determining, for each of the plurality of nodes, a speed associated with the node, where the speed is determined based on the parameters represented by the node, and
directing the plurality of nodes within the DAG based on the speed associated with each node; and
calculating one or more settings for the device, utilizing the plurality of nodes included within the DAG.

16. The system of claim 15 , wherein the processor is coupled to memory via a bus.

Assignees

• Spitzer John F
• Vinogradov Oleg Vyacheslavovich
• Grebenkin Sergey Sergeevich
• Nvidia Corp

Inventors

• Spitzer John F
• Vinogradov Oleg Vyacheslavovich
• Grebenkin Sergey Sergeevich

Classifications

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G09G5/363

  Graphics controllers · CPC title

• G06F17/2247

  Physics · mapped topic