Initializing processor cores in a multiprocessor system

Patent metadata

Field	Value
Publication number	US-9250920-B2
Application number	US-201313781459-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Nov 26, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method for initializing processor cores in a multiprocessor system. The method includes a microcontroller initializing a first processor utilizing a common initialization image for all processor cores within the first processor. The first processor detects and executes system firmware. All remaining processors are initialized utilizing the common initialization image. The executing firmware detects a system configuration of the multiprocessor system. A customized processor initialization image for each of the processor cores in the multiprocessor system is generated and stored to a storage device. The processor cores are triggered to enter a power save state in which all initialization settings of the processor cores are lost. In response to all the processor cores entering the power save state, the first processor core of the first processor is re-initialized using a first customized initialization image generated for the first processor core.

First claim

What is claimed is:

1. A computer-implemented method of initializing a plurality of processor cores of a plurality of processors in a multiprocessor system, the method comprising:
a microcontroller initializing a first processor of the plurality of processors utilizing a common initialization image, wherein the common initialization image is usable to initialize all processor cores within the first processor, and wherein the microcontroller is separate from the plurality of processors;
in response to initializing the first processor using the common initialization image, the microcontroller retrieving and loading a system firmware for execution on the first processor;
initializing all remaining processors utilizing the common initialization image;
detecting, via the executing firmware, a system configuration of the multiprocessor system, wherein detecting the system configuration further comprises probing, within the multiprocessor system, at least one of: one or more inter-processor input/output (I/O) busses between the plurality of processor cores, a system memory, one or more local memories, and one or more other processing components;
for each of the processor cores in the multiprocessor system, generating a customized processor initialization image based on settings and parameters identified in the system configuration for that processor core;
storing the customized processor initialization images to a memory location within a storage device;
triggering all of the processor cores to enter a power save state in which all initialization settings of all of the processor cores are lost; and
in response to the microcontroller detecting that all of the processor cores have entered the power save state, the microcontroller re-initializing at least a first processor core of the first processor using a first customized initialization image generated for the first processor core, wherein the microcontroller loads the first customized initialization image from the memory location in the storage device.

2. The method of claim 1 , wherein the initializing of the first processor utilizing the common initialization image comprises detecting a powering on of the first processor and initializing the processor cores of the first processor in response to detecting the powering on.

3. The method of claim 1 , further comprising the microcontroller:
in response to detecting that all of the processor cores have entered the power save state, the microcontroller issuing an interrupt to the first processor core of the first processor that wakes the first processor core; and
reading the first customized initialization image for the first processor core of the first processor from the storage device.

4. The method of claim 3 , further comprising:
issuing an interrupt to each remaining processor cores within the multiprocessor system;
the microcontroller reading, from the storage device, customized initialization images for each of the remaining processor cores; and
the microcontroller initializing all of the remaining processor cores with their respective customized initialization images.

5. The method of claim 1 , further comprising:
in response to completing storing of the custom initialization images, transmitting a storage location address associated with each of the customized initialization images to the microcontroller, wherein the storage location address identifies a location in the storage device at which the customized initialization images are maintained.

6. The method of claim 1 , further comprising: in response to triggering all of the processor cores to enter the power save state, the microcontroller continually polling all of the processor cores to determine a current power state of each of the cores; and
the microcrontoller triggering initialization of the first processor only responsive to all the processor cores having the power save state as the current power state.

7. The method of claim 1 , further comprising:
notifying the microcontroller of a pending power save command prior to triggering all of the processor cores to enter the power save state.

8. The method of claim 1 , further comprising:
identifying a master processor and a master core in the multiprocessor system, wherein the master core of the master processor receives an interrupt from the microcontroller responsive to detecting that all of the processor cores have entered the power save state.

9. The method of claim 1 , further comprising:
receiving at least a portion of the system configuration via a user input setting; and
generating the customized processor initialization image for each of the processor cores in the multiprocessor system based at least partially on the portion of the system configuration received via the user input setting.

10. The method of claim 1 , wherein the one or more other processing components include at least one of one or more other processors and one or more other microcontrollers and wherein the microcontroller controls the operation of portions of the plurality of processors during start-up or initialization.

11. The method of claim 1 , wherein the one or more local memories are probed using serial presence detect (SPD).

12. The method of claim 11 , further comprising:
in response to probing the one or more local memories, detecting at least one type of memory and at least one of:
memory timing parameters for the at least one type of memory, wherein the memory timing parameters include a column address strobe (CAS) latency of the at least one type of memory;
a manufacturer of the at least one type of memory; and
a serial number of each memory module of the at least one type of memory.

13. The method of claim 1 , further comprising:
determining the memory location by reading a basic address register (BAR) within the microcontroller; and
updating the BAR to point to the memory location.

14. The method of claim 1 , wherein the common initialization image is stored in one of a flash memory and an electrically erasable programmable read only memory (EEPROM) separate from the storage device.

15. The method of claim 1 , wherein the system configuration comprises a configuration of hardware in the multiprocessor system.

Assignees

• IBM

Inventors

• Sanner Iii David Dean
• Smith Jeshua Daniel
• Still Gregory Scott
• Williams Iii Alwood Patrick

Classifications

• G06F9/4405 Primary

  Initialisation of multiprocessor systems · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4403

  Processor initialisation · CPC title