Array substrate and liquid crystal display

Patent metadata

Field	Value
Publication number	US-9250477-B2
Application number	US-201213524144-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 17, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

An embodiment of the present disclosure provides an array substrate, and the array substrate including: at least a data line and at least a gate line; and a plurality of pixel units defined by the data line and the gate line. Each of the plurality of pixel units includes a thin film transistor, a first electrode and a second electrode, and the first electrode and the second electrode overlap each other and are insulated from each other and the second electrode is positioned above the first electrode. An alignment film is formed on a surface of the array substrate, a direction of the second electrode and one side of the array substrate form a predetermined angle and a rubbing direction of the alignment film is parallel to the one side of the array substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
at least a data line and at least a gate line; and
a plurality of pixel units defined by the data line and the gate line, wherein each of the plurality of pixel units comprises a thin film transistor, a first electrode and a second electrode, the first electrode and the second electrode overlap each other and are insulated from each other, and the second electrode is positioned above the first electrode, and
wherein an alignment film is formed on a surface of the array substrate, and a rubbing direction of the alignment film is parallel to a side of the array substrate on a side of the data line, wherein the second electrode is rectangular and comprises a plurality of stripe slits in parallel with each other and the stripe slits form a predetermined angle which is larger than 15 degrees and which is equal to or smaller than 20 degrees respective to the side of the array substrate on the side of the data line; wherein an end portion of each stripe slit has an arc shape.

2. The array substrate according to the claim 1 , wherein the second electrode is connected to a drain electrode of the thin film transistor.

3. The array substrate according to the claim 1 , wherein the first electrode is connected to a drain electrode of the thin film transistor.

4. The array substrate according to the claim 1 , wherein the first electrode has a pattern.

5. A liquid crystal display, comprising:
an array substrate; and
a color filter substrate;
wherein the array substrate and the color filter substrate are positioned opposite to each other to form a liquid crystal cell, alignment films are respectively formed on inner surfaces of the array substrate and the color filter substrate, and the array substrate comprises:
at least a data line and at least a gate line; and
a plurality of pixel units defined by the data line and the gate line, wherein each of the plurality of pixel units comprises a thin film transistor, a first electrode and a second electrode, and the first electrode and the second electrode overlap each other and are insulated from each other, and the second electrode is positioned above the first electrode, and
wherein an alignment film is formed on a surface of the array substrate, a rubbing direction of the alignment film is parallel to a side of the array substrate on a side of the data line; wherein a rubbing direction of the alignment film on the color filter substrate is identical to the rubbing direction of the alignment film on the array substrate, wherein the second electrode is rectangular and comprises a plurality of stripe slits in parallel with each other and the stripe slits form a predetermined angle which is larger than 15 degrees and which is equal to or smaller than 20 degrees respective to the side of the array substrate on the side of the data line; wherein an end portion of each stripe slit has an arc shape.

6. The liquid crystal display according to the claim 5 , wherein the second electrode is connected to a drain electrode of the thin film transistor.

7. The liquid crystal display according to the claim 5 , wherein the first electrode is connected to a drain electrode of the thin film transistor.

8. The liquid crystal display according to the claim 5 , wherein the first electrode has a pattern.

9. The array substrate according to the claim 1 , wherein one segment of the data line corresponds to each of the plurality of pixel units is parallel to the direction of the second electrode in the pixel unit and the data line is formed in a continuous zigzag shape.

10. The array substrate according to the claim 2 , wherein one segment of the data line corresponds to each of the plurality of pixel units is parallel to the direction of the second electrode in the pixel unit and the data line is formed in a continuous zigzag shape.

11. The array substrate according to the claim 3 , wherein one segment of the data line corresponds to each of the plurality of pixel units is parallel to the direction of the second electrode in the pixel unit and the data line is formed in a continuous zigzag shape.

12. The liquid crystal display according to the claim 5 , wherein one segment of the data line corresponds to each of the plurality of pixel units is parallel to the direction of the second electrode in the pixel unit and the data line is formed in a continuous zigzag shape.

13. The liquid crystal display according to the claim 6 , wherein one segment of the data line corresponds to each of the plurality of pixel units is parallel to the direction of the second electrode in the pixel unit and the data line is formed in a continuous zigzag shape.

14. The liquid crystal display according to the claim 7 , wherein one segment of the data line corresponds to each of the plurality of pixel units is parallel to the direction of the second electrode in the pixel unit and the data line is formed in a continuous zigzag shape.

Assignees

• Chen Dong
• Dong Xue
• Li Cheng
• Beijing Boe Optoelectronics

Inventors

• Chen Dong
• Dong Xue
• Li Cheng

Classifications

• G02F1/133707 Primary

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

• G02F2001/134381

  Physics · mapped topic

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/134381

  Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates · CPC title