Sensor arrangement for speed measurement

Patent metadata

Field	Value
Publication number	US-9250258-B2
Application number	US-201113699854-A
Country	US
Kind code	B2
Filing date	Jun 10, 2011
Priority date	Jun 10, 2010
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A sensor array including an electronic control unit and a speed sensor that has at least one sensor element. The speed sensor and the electronic control unit are interconnected by at least one line. The speed sensor includes a signal processing circuit which is designed in such a way as to obtain at least one digital frequency signal from the output signal of the sensor element, the at least one digital frequency signal being encoded in a data item, being stored in at least one first memory unit, and being transmitted to the electronic control unit.

First claim

The invention claimed is:

1. A sensor arrangement comprising:
an electronic control unit including a clock generator for generating a trigger signal; and
a speed sensor connected to the electronic control unit by at least one line,
wherein the speed sensor includes a first memory unit, at least one sensor element and a signal processing circuit, the signal processing circuit is configured to obtain from the at least one sensor-element at least one digital frequency signal, which is encoded in a data word and stored in the first memory unit and transmitted to the electronic control unit over the at least one line in response to receiving the trigger signal from the electronic control unit over the at least one line.

2. The sensor arrangement as claimed in claim 1 , wherein the speed sensor comprises a sensor clock generator unit, where the digital frequency signal is scaled by and/or is dependent on said sensor clock generator unit.

3. The sensor arrangement as claimed in claim 2 , wherein at least the sensor clock generator unit is integrated together with the signal processing circuit on a chip.

4. The sensor arrangement as claimed in claim 2 , wherein at least the sensor clock generator unit is integrated together with the signal processing circuit on a chip as an RC oscillator.

5. The sensor arrangement as claimed in claim 2 , wherein the electronic control unit comprises an ECU clock generator unit.

6. The sensor arrangement as claimed in claim 2 , wherein the electronic control unit comprises an ECU clock generator unit comprising a crystal oscillator.

7. The sensor arrangement as claimed in claim 5 , wherein the speed sensor successively transmits data words to the electronic control unit at a sensor transmit frequency, wherein the sensor transmit frequency depends on the clock frequency of the sensor clock generator unit, and wherein the electronic control unit detects the sensor transmit frequency and hence, taking into account the clock frequency of the ECU clock generator unit, scales or corrects at least one piece of frequency information of a data word.

8. The sensor arrangement as claimed in claim 5 , wherein the electronic control unit transmits data request signals to the speed sensor at defined times or at a defined clock rate, and said speed sensor transmits as a response to each of said data request signals a data word to the electronic control unit.

9. The sensor arrangement as claimed in claim 8 , wherein the electronic control unit sends the data request signals to the speed sensor in a defined manner on the basis of the clock frequency of its ECU clock generator unit, at a constant request frequency, and wherein the speed sensor detects the request frequency, and adjusts or corrects the frequency information or the frequency signal of a data word.

10. The sensor arrangement as claimed in claim 8 , wherein the electronic control unit sends the data request signals to the speed sensor in a defined manner on the basis of the clock frequency of its ECU clock generator unit, at a constant request frequency, and wherein the speed detects the request frequency, and adjusts or corrects the frequency information or the frequency signal of a data word according to a ratio of the request frequency to the clock frequency of its own sensor clock generator unit.

11. The sensor arrangement as claimed in claim 8 , wherein the electronic control unit sends the data request signals to the speed sensor in a defined manner on the basis of the clock frequency of its ECU clock generator unit, at a constant request frequency, and wherein the speed sensor detects the request frequency, and adjusts or corrects the frequency information or the frequency signal of each data word according to a ratio of the request frequency to the clock frequency of its own sensor clock generator unit.

12. The sensor arrangement as claimed in claim 1 , wherein a data word comprises at least one or a plurality of the following pieces of information:
a piece of frequency information or the digital frequency signal,
a piece of angle information,
a piece of internal status information from the speed sensor,
a piece of external status information from at least one external component connected to the speed sensor,
a piece of identification information from the speed sensor itself and/or
detailed measurement information.

13. The sensor arrangement as claimed claim 1 , wherein the speed sensor comprises at least one sensor element and an analog-to-digital converter, which digitizes the sensor-element output signals, wherein the speed sensor comprises a Costas loop unit, which is connected to the output of the analog-to-digital converter, and wherein the analog-to-digital converter is in the form of a sigma-delta modulator.

14. The sensor arrangement as claimed in claim 13 , wherein the Costas loop unit provides at least a frequency output signal (f NCO ) or a phase output signal (φ NCO ) or a frequency output signal (f NCO ) and a phase output signal (φ NCO ), each on the basis of the sensor-element output signal.

15. The sensor arrangement as claimed in claim 13 , wherein the output of the analog-to-digital converter, which provides a bit stream, is connected in each case to a first multiplier and to a second multiplier, wherein additionally the first multiplier and the second multiplier are each fed with a clock signal from a sensor clock generator unit, wherein the clock signals (sin, cos) fed to the first multiplier and the second multiplier are offset in phase by 90° with respect to one another, wherein the output signal from the first multiplier and the second multiplier is fed in each case to a low-pass filter, the outputs of which are each fed to a common phase detector unit, which is connected on the output side to a controller unit, the output of which is connected to the sensor clock generator unit.

16. The sensor arrangement as claimed in claim 15 , wherein the sensor clock generator unit is in the form of a numerically controlled oscillator, wherein said clock generator unit provides the frequency output signal (f NCO ) and/or the phase output signal (φ NCO ) as output signals from the Costas loop unit.

17. The sensor arrangement as claimed in claim 15 , wherein the output signal from the phase detector unit and the phase output signal (φ NCO ) from the sensor clock generator unit are summated, in a summator, thereby generating a corrected phase signal (φ) that forms an output signal from the Costas loop unit, alternatively or additionally to the phase output signal (φ NCO ) from the sensor clock generator unit.

18. The sensor arrangement as claimed in claim 13 , wherein the speed sensor comprises an output circuit to which are fed from the Costas loop unit the frequency output signal (f NCO ) from the sensor clock generator unit and the phase output signal (φ NCO ) from the sensor clock generator unit and/or the corrected phase signal (φ), wherein the output circuit comprises at least one driver stage for transmitting the output signal from the speed sensor over at least one line, and comprises a logic unit, which is used to provide the output signal from the output circuit such that it has defined signal properties as a defined interface, wherein the logic unit is programmable and/or switchable, so that the output signal from the output circuit and hence from the speed sensor is adaptable to different interface requirements.

19. The sensor arrangement as claimed in claim 18 , wherein the logic unit comprises a compensation device, which contains at least one

Assignees

• Acker Heinrich
• Continental Teves Ag & Co Ohg

Inventors

• Acker Heinrich

Classifications

• H04Q2209/84

  Measuring functions · CPC title

• G01P3/00 Primary

  Measuring linear or angular speed; Measuring differences of linear or angular speeds (G01P5/00 - G01P11/00 take precedence; {direction and speed indication G01P13/045}; counting mechanisms G06M) · CPC title

• H04Q9/00

  Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom · CPC title

• G01P3/489

  Digital circuits therefor · CPC title

• G01D5/24404 Primary

  Interpolation using high frequency signals · CPC title