Triple conversion gain image sensor pixels

Patent metadata

Field	Value
Publication number	US-9247170-B2
Application number	US-201314031797-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	Sep 20, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

An image sensor having pixel circuitry operable in multiple gain modes is provided. The pixel circuitry may include first and second floating diffusion (FD) regions, a first photodiode coupled to the first FD region via a first transfer gate, a second photodiode coupled to the first FD region via a second transfer gate, a third photodiode coupled to the second FD region via a third transfer gate, and a fourth photodiode coupled to the second FD region via a fourth transfer gate. The first FD region may be coupled to the second FD region via first and second control transistors. The control transistors may be connected to a shared reset transistor. During readout, both control transistors may be deactivated to provide a high gain mode, only one transistor may be activated to provide an intermediate gain mode, or both control transistors may be activated to provide a low gain mode.

First claim

What is claimed is:

1. Image sensor pixel circuitry, comprising:
a first floating diffusion region;
a second floating diffusion region; and
first and second control transistors coupled in series between the first and second floating diffusion regions, wherein the first control transistor has a first source-drain terminal that is coupled to the first floating diffusion region and a second source-drain terminal that is coupled to an intermediate node, and wherein the second control transistor has a first source-drain terminal that is coupled to the second floating diffusion region and a second source-drain terminal that is coupled to the intermediate node; and
a reset transistor having a first source-drain terminal that is coupled to the intermediate node and a second source-drain terminal at which a reset voltage is applied.

2. The image sensor pixel circuitry defined in claim 1 , further comprising:
a first plurality of photosensitive elements coupled to the first floating diffusion region; and
a second plurality of photosensitive elements coupled to the second floating diffusion region.

3. The image sensor pixel circuitry defined in claim 2 , further comprising:
a first plurality of charge transfer transistors coupled between the first plurality of photosensitive elements and the first floating diffusion region; and
a second plurality of charge transfer transistors coupled between the second plurality of photosensitive elements and the second floating diffusion region.

4. The image sensor pixel circuitry defined in claim 1 , further comprising:
a first control line on which a first conversion gain mode control signal is provided, wherein the first control transistor has a gate terminal that is coupled to the first control line; and
a second control line on which a second conversion gain mode control signal is provided, wherein the second control transistor has a gate terminal that is coupled to the second control line.

5. The image sensor pixel circuitry defined in claim 1 , wherein the image sensor pixel circuitry is operable in a first gain mode during which both first and second control transistors are turned off, a second gain mode during which a selected one of the first and second control transistors is turned on, and a third gain mode during which the first and second control transistors are turned on.

6. The image sensor pixel circuitry defined in claim 1 , further comprising:
a power supply line;
a shared column output line; and
a source follower transistor having a drain terminal coupled to the power supply line, a gate terminal coupled to the first floating diffusion region, and a source terminal directly connected to the shared column output line.

7. A method for operating image sensor pixel circuitry that includes first and second floating diffusion nodes and first and second control transistors coupled in series between the first and second floating diffusion nodes, comprising:
configuring the image sensor pixel circuitry in a first gain mode by turning off the first and second control transistors;
configuring the image sensor pixel circuitry in a second gain mode by turning on a selected one of the first and second control transistors;
configuring the image sensor pixel circuitry in a third gain mode by turning on the first and second control transistors; and
with a reset transistor that is coupled between the first and second floating diffusion nodes, resetting the first floating diffusion node via the first control transistor and resetting the second floating diffusion node via the second control transistor.

8. The method defined in claim 7 , further comprising:
providing a first conversion gain during the first gain mode;
providing a second conversion gain during the second gain mode; and
providing a third conversion gain during the third gain mode, wherein the first conversion gain is greater than the second conversion gain, and wherein the second conversion gain is greater than the third conversion gain.

9. The method defined in claim 7 , further comprising:
transferring charge from a plurality of photosensitive elements to the first floating diffusion node.

10. The method defined in claim 7 , wherein the image sensor pixel circuitry further includes a source follower transistor having a gate coupled to the first floating diffusion node, the method further comprising:
turning off the source follower transistor by using the reset transistor to pass a low voltage signal to the first floating diffusion node via the first control transistor.

11. The method defined in claim 7 , further comprising:
simultaneously transferring charge from a first photosensitive element to the first floating diffusion node and transferring charge from a second photosensitive element to the second floating diffusion node.

12. The method defined in claim 7 , wherein configuring the image sensor pixel circuitry in the third gain mode comprises shorting the first and second floating diffusion nodes.

13. The method defined in claim 7 , wherein the image sensor pixel circuitry further includes a source follower transistor having a gate coupled to the first floating diffusion node, the method further comprising:
outputting an image signal associated with the first floating diffusion node using the source follower transistor without a row select transistor.

14. A system, comprising:
a central processing unit;
memory;
a lens;
input-output circuitry; and
an imaging device having an image sensor pixel that includes:
a first floating diffusion region;
a first photodiode that is coupled to the first floating diffusion region via a first charge transfer transistor;
a second floating diffusion region;
a second photodiode that is coupled to the second floating diffusion region via a second charge transfer transistor;
first and second control transistors coupled in series between the first and second floating diffusion regions, wherein the image sensor pixel is operable to perform low gain mode readout operations during which both the first and second control transistors are turned on, and wherein only one of the first and second charge transfer transistors is turned on during the low gain mode readout operations; and
a reset transistor coupled between the first and second floating diffusion regions, wherein the reset transistor resets the first floating diffusion region via the first control transistor and resets the second floating diffusion region via the second control transistor.

15. The system defined in claim 14 , wherein the image sensor pixel is operable to perform high gain mode readout operations during which both the first and second control transistors are turned off.

16. The system defined in claim 14 , wherein the image sensor pixel is operable to perform medium gain mode readout operations during which only one of the first and second control transistors is turned on, wherein the image sensor pixel provides a first conversion gain when performing the high gain mode readout operations, a second conversion gain when performing the low gain mode readout operations, and a third conversion gain when performing the medium gain mode readout operations, and wherein the third conversion gain is less than the first conversion gain and greater than the second conversion gain.

Assignees

• Semiconductor Components Ind

Inventors

• Komori Hirofumi
• Gao Wei
• Perez Paul
• Tian Hui
• Zhao Xia

Classifications

• H04N25/59 Primary

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N5/37457

  Electricity · mapped topic