Apparatus and methods for input bias current reduction

Patent metadata

Field	Value
Publication number	US-9246484-B2
Application number	US-201414201234-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 7, 2014
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

First claim

What is claimed is:

1. An electronic circuit comprising:
a first input terminal and a second input terminal;
an input circuit including a first input and a second input;
a plurality of input switches controlled by one or more clock signals, wherein the plurality of input switches comprises:
a first input switch electrically connected between the first input terminal and the first input of the input circuit, and
a second input switch electrically connected between the second input terminal and the second input of the input circuit; and

a charge compensation circuit comprising a first output and a second output, wherein the charge compensation circuit is configured to compensate for charge injected by the plurality of input switches associated with at least one transition of the one or more clock signals.

2. The electronic circuit of claim 1 , wherein the first output of the charge compensation circuit is electrically connected to the first input of the input circuit, and wherein the second output of the charge compensation circuit is electrically connected to the second input of the input circuit.

3. The electronic circuit of claim 1 , wherein the first output of the charge compensation circuit is electrically connected to the first input terminal, and wherein the second output of the charge compensation circuit is electrically connected to the second input terminal.

4. The electronic circuit of claim 1 , wherein the charge compensation circuit is configured to receive a charge control signal, wherein a value of the charge control signal controls a first amount of charge generated at the first output of the charge compensation circuit and a second amount of charge generated at the second output of the charge compensation circuit.

5. The electronic circuit of claim 4 , further comprising a programmable memory configured to control the value of the charge control signal based on data stored therein.

6. The electronic circuit of claim 4 , further comprising an input current detection circuit configured to generate the charge control signal, wherein the input current detection circuit is configured to determine the value of the charge control signal based on observing an input bias current of the electronic circuit for each of a plurality of test values of the charge control signal.

7. The electronic circuit of claim 4 , wherein the charge compensation circuit comprises:
a first logic circuit having an input configured to receive a charge compensation clock signal and an output;
a first capacitor structure having a first end electrically connected to the output of the first logic circuit and a second end electrically connected to the first input of the input circuit;
a second logic circuit having an input configured to receive the charge compensation clock signal and an output; and
a second capacitor structure having a first end electrically connected to the output of the second logic circuit and a second end electrically connected to the second input of the input circuit.

8. The electronic circuit of claim 7 , wherein the charge compensation circuit further comprises:
a digital-to-analog converter (DAC) configured to receive the charge control signal and to generate a first DAC voltage and a second DAC voltage based on the value of the charge control signal,
wherein the first logic circuit is powered in part by the first DAC voltage, and
wherein the second logic circuit is powered in part by the second DAC voltage.

9. The electronic circuit of claim 7 , wherein the first logic circuit comprises a first inverter, and wherein the second logic circuit comprises a second inverter.

10. The electronic circuit of claim 7 , wherein the charge compensation circuit further comprises:
a DAC configured to receive the charge control signal and to generate a first tuning voltage and a second tuning voltage based on the value of the charge control signal,
wherein the first capacitor structure comprises a first variable capacitor, wherein a capacitance of the first variable capacitor is tunable by the first tuning voltage, and
wherein the second capacitor structure comprises a second variable capacitor, wherein a capacitance of the second variable capacitor is tunable by the second tuning voltage.

11. The electronic circuit of claim 7 ,
wherein the charge control signal comprise a plurality of bits,
wherein the first capacitor structure comprises a first capacitor array, wherein an active capacitance of the first capacitor array is selectable by a first portion of the plurality of bits, and
wherein the second capacitor structure comprises a second capacitor array, wherein an active capacitance of the second capacitor array is selectable by a second portion of the plurality of bits.

12. The electronic circuit of claim 1 ,
wherein the first input switch comprises a first field-effect transistor (FET) having a gate configured to receive a first clock signal of the one or more clock signals, a drain electrically connected to the first input terminal, and a source electrically connected to the first input of the input circuit,
wherein the second input switch comprises a second FET having a gate configured to receive the first clock signal, a drain electrically connected to the second input terminal, and a source electrically connected to the second input of the input circuit.

13. The electronic circuit of claim 12 , wherein the plurality of input switches further comprises:
a third FET having a gate configured to receive a second clock signal of the one or more clock signals, a drain electrically connected to the second input terminal, and a source electrically connected to the first input of the input circuit; and
a fourth FET having a gate configured to receive the second clock signal, a drain electrically connected to the first input terminal, and a source electrically connected to the second input of the input circuit,
wherein the input circuit comprises an amplification circuit of a chopper amplifier.

14. The electronic circuit of claim 13 , wherein the charge compensation circuit comprises:
a plurality of logic circuits comprising a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit;
a plurality of capacitor structures comprising a first capacitor structure, a second capacitor structure, a third capacitor structure, and a fourth capacitor structure,
wherein the first capacitor structure includes a first end electrically connected to an output of the first logic circuit and a second end electrically connected to the first input of the input circuit,
wherein the second capacitor structure includes a first end electrically connected to an output of the second logic circuit and a second end electrically connected to the second input of the input circuit,
wherein the third capacitor structure includes a first end electrically connected to an output of the third logic circuit and a second end electrically connected to the first input of the input circuit, and
wherein the fourth capacitor structure includes a first end electrically connected to an output of the fourth logic circuit and a second end electrically connected to the second input of the input circuit.

15. The electronic circuit of claim 14 ,
wherein the first logic circuit further includes an input configured to receive a first charge compensation clock signal of a first polarity,
wherein the second logic circuit further includes an input configured to receive the first charge compensation clock signal,
wherein the third logic circuit further includes an input configured to receive a second char

Assignees

• Analog Devices Inc

Inventors

• Kusuda Yoshinori

Classifications

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03F3/387

  with semiconductor devices only · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03F2203/45606

  the IC comprising one or more parallel resonance circuits · CPC title