Power switches for aircraft

Patent metadata

Field	Value
Publication number	US-9246482-B2
Application number	US-201113082137-A
Country	US
Kind code	B2
Filing date	Apr 7, 2011
Priority date	Apr 7, 2010
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

The present invention relates generally to power switches for aircraft. According to a first aspect, the present invention provides an integrated solid state power switch for fault protection in an aircraft power distribution system. The integrated solid state power switch is formed of semiconductor material that provides a field effect transistor (FET) channel that is operable during normal device operation to provide an operating current flow path and a bipolar transistor channel that is operable during device overload conditions to provide an overload current flow path. A method for manufacturing such an integrated solid state power switch is also described. Various embodiments of the invention provide automatic overload current protection for aircraft systems without the need to use bulky switches or heavy cooling equipment.

First claim

What is claimed is:

1. An integrated solid state power switch for fault protection in an aircraft power distribution system, the integrated solid state power switch being formed of semiconductor material comprising:
a gate structure;
a single channel layer electrically coupled to the gate structure, wherein the single channel layer comprises:
a field effect transistor (FET) channel that is operable during normal device operation to provide an operating current flow path; and
a bipolar transistor channel that is operable during device overload conditions to provide an overload current flow path;

a substrate layer comprising P-type IGBT doped collector regions surrounding at least one N-type MOSFET drain region wherein the single channel layer is between the gate structure and the at least one-type MOSFET drain region; and
a source/emitter physically connected to a side of the single channel layer;
wherein at least one MOSFET structure and at least one IGBT structure occupy substantially the same volume vertically between the substrate layer and the gate structure to form at least one vertically integrated hybrid device.

2. The integrated solid state power switch of claim 1 , wherein the operating current flow path has maximal conductivity when the solid state power switch operates with a normal current load having a magnitude I normal , and overload current flow path has maximal conductivity when the solid state power switch operates with a fault current load having a magnitude I fault .

3. The integrated solid state power switch of claim 2 , wherein I fault >n.I normal , n being an integer having a value greater than one.

4. The integrated solid state power switch of claim 1 , wherein the field effect transistor (FET) channel is provided by at least one metal-oxide-silicon field effect transistor (MOSFET) structure.

5. The integrated solid state power switch of claim 1 , wherein the bipolar transistor channel is provided by at least one insulated gate bipolar transistor (IGBT) structure.

6. The integrated solid state power switch of claim 1 , wherein the single channel layer is between the gate structure and the P-type IGBT doped collector regions.

7. The integrated solid state power switch of claim 1 , wherein a ratio (Δ) of a number MOSFET structures (m) to a number of IGBT structures (i) is greater than 1:1.

8. The integrated solid state power switch of claim 7 , wherein the ratio (Δ) is 3:1.

9. The integrated solid state power switch of claim 1 , wherein the semiconductor material is silicon.

10. The integrated solid state power switch of claim 1 , formed on a single semiconductor wafer.

11. The integrated solid state power switch of claim 1 , wherein the integrated solid state power switch is a high power device.

12. The integrated solid state power switch of claim 1 , wherein the gate structure comprises a single gate device.

13. The integrated solid state power switch of claim 1 , comprising a ring shaped electrical contact formed on a face of the semiconductor material opposite the substrate layer and concentrically aligned with a center of the MOSFET drain region, wherein the contact comprises a radially outermost N+-type ring of material having an exposed surface, a radially innermost concentric P-type ring of material in contact with the channel layer, the outermost ring of material and the face of the semiconductor material opposite the substrate layer, and a third concentric ring of N−-type material in contact with the face of the semiconductor material opposite the substrate layer, the outermost ring of material and the innermost ring of material.

14. The integrated solid state power switch of claim 13 , wherein the gate structure comprises a layer of oxide material overlapping the innermost ring of material and the third ring of material of the contact where they are exposed at the face of the semiconductor material opposite the substrate layer.

15. The integrated solid state power switch of claim 14 , comprising a metallic layer of material over the oxide material to form a gate contact of the gate structure.

Assignees

• Shipley Adrian
• Stevens Martin James
• Mawby Phil
• Bryant Angus
• Ge Aviat Systems Ltd

Inventors

• Shipley Adrian
• Stevens Martin James
• Mawby Phil
• Bryant Angus

Classifications

• H03K17/082 Primary

  by feedback from the output to the control circuit · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/156

  Drain regions of DMOS transistors · CPC title

• H10D62/124 Primary

  Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions · CPC title