Memory devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9246083-B2
Application number	US-201414498465-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Feb 29, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

First claim

What is claimed is:

1. A method of fabricating a memory device, comprising:
forming a plurality of first contacts connected to a plurality of peripheral transistors on a substrate;
forming a plurality of data storages two-dimensionally arranged on a cell region of the substrate;
forming an interlayered dielectric covering uppermost surfaces of the plurality of first contacts and uppermost surfaces of the plurality of data storages;
patterning the interlayered dielectric to form a plurality of first trenches exposing the uppermost surfaces of the plurality of data storages;
patterning the interlayered dielectric to form a plurality second trenches exposing the uppermost surfaces of the plurality of first contacts;
forming a plurality of first bit lines connected to the plurality of data storages in the plurality of first trenches; and
forming a plurality of second bit lines connected to the plurality of first contacts in the plurality of second trenches,
wherein the plurality of first trenches and the plurality of second trenches are formed using different etching processes.

2. The method of claim 1 , wherein the plurality of second trenches each have a lowermost surface lower than a lowermost surface of each of the plurality of data storages.

3. The method of claim 1 , wherein the plurality of first and second bit lines are formed at a process temperature lower than a process temperature used to form the plurality of first contacts.

4. The method of claim 1 , wherein forming the plurality of first and second bit lines includes,
forming a conductive layer filling the plurality of first and second trenches; and
performing a planarization process to expose the interlayered dielectric.

5. A method of fabricating a memory device, comprising:
forming a first contact electrically connected to a peripheral transistor in a peripheral circuit region of a substrate;
forming a data storage in a cell region of the substrate;
forming an interlayered dielectric layer covering uppermost surfaces of the first contact and uppermost surfaces of the data storage;
forming a first trench exposing the uppermost surfaces of the data storage by patterning the interlayered dielectric layer only over the cell region using a first etching process;
forming a second trench exposing the uppermost surfaces of the first contact by patterning the interlayered dielectric layer only over the peripheral circuit region using a second etching process;
forming a first bit line connected to the data storage in the first trench; and
forming a second bit line contacting the first contact in the second trench.

6. The method of claim 5 , wherein the data storage includes a magnetic tunnel junction.

7. The method of claim 6 , wherein a lowermost surface of the second bit line is lower than a lowermost surface of the magnetic tunnel junction.

8. The method of claim 6 , further comprising:
providing a cell transistor in the cell region electrically connected to the data storage via a second contact, prior to forming the data storage,
wherein the first contact and the second contact are formed of different materials.

9. The method of claim 8 , wherein the second contact is formed of a material containing tungsten.

10. The method of claim 1 , wherein the plurality of peripheral transistors each include a source/drain region, and
wherein the plurality of first contacts are each connected to the source/drain region of one of the plurality of peripheral transistors.

11. The method of claim 5 , wherein the peripheral transistor includes a source/drain region, and
wherein the first contact is connected to the source/drain region of the peripheral transistor.

12. The method of claim 2 , wherein the plurality of second bit lines each have an uppermost surface that is higher than the uppermost surface of each of the plurality of data storages.

13. The method of claim 7 , wherein an uppermost surface of the second bit line is higher than the uppermost surface of the data storage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kilho
• Kim Ki Joon
• Park Se Woong

Classifications

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10D48/40

  Devices controlled by magnetic fields · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10B99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10B12/485 Primary

  Bit line contacts · CPC title