Photovoltaic cells having metal wrap through and improved passivation

Patent metadata

Field	Value
Publication number	US-9246044-B2
Application number	US-79262410-A
Country	US
Kind code	B2
Filing date	Jun 2, 2010
Priority date	Dec 3, 2007
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A photovoltaic device is disclosed. In one aspect, the device is formed in a semiconductor substrate. It has a radiation receiving front surface and a rear surface. The device may have a first region of one conductivity type, a second region with the opposite conductivity type adjacent to the front surface, and an antireflection layer. The rear surface is covered by a dielectric layer covering also an inside surface of the via. The front surface has current collecting conductive contacts. The rear surface has conductive contacts extending through the dielectric. A conductive path is in the via for photogenerated current from the front surface. By having the dielectric all over, no aligning and masking is needed. The same dielectric serves to insulate, provide thermal protection, and helps in surface and bulk passivation. It also avoids the need for a junction region near the via, hence reducing unwanted recombination currents.

First claim

What is claimed is:

1. A photovoltaic device comprising:
a semiconductor layer doped with a bulk dopant of a first type and having an emitter region doped with a dopant of a second type formed only at a front surface configured to receive impinging light, the semiconductor layer further having a rear surface opposite to the front surface;
a front contact configured to collect current from the front surface;
a rear bus bar formed at a rear side of the device and electrically connected to the front contact for collecting the current from the front surface through the front contact;
a via formed through the semiconductor layer, such that an inside surface of the via is not doped with the dopant of the second type beyond the depth of the emitter region, the via having a conductive path formed therethrough and over the inner surface for coupling the front contact to the rear bus bar;
a dielectric layer formed on the rear surface of the semiconductor layer and further on an inside surface of the via; and
a back contact for the rear surface of the semiconductor layer, the back contact formed through a hole patterned through the dielectric layer,
wherein the dielectric layer has a thickness between about 100 nm and 5000 nm to electrically insulate the conductive path from the inside surface of the via.

2. The device of claim 1 , wherein the dielectric layer comprises a low quality oxide layer comprising any one of APCVD oxide, pyrolithic oxide, spin-on oxide, spray-on oxide, dip oxide, a silicon oxide, TiO 2 , TiO 2 deposited by solgel, or Al 2 O 3 /TiO 2 pseudobinary alloys (PBAs).

3. The device of claim 2 , wherein the device further comprises a back side passivation layer over the dielectric layer.

4. The device of claim 3 , wherein the back side passivation layer extends at least part of the way into the via.

5. The device of claim 4 , wherein the back side passivation layer comprises hydrogenated SiN.

6. The device of claim 1 , wherein the dielectric layer extends over the rear surface around the via without being patterned and aligned to the via.

7. A method of manufacturing a photovoltaic device having a semiconductor layer doped with a bulk dopant of a first type and having a front surface for receiving impinging light and a rear surface opposite to the front surface, the method comprising:
forming an emitter region doped with a dopant of a second type only at the front surface;
forming a via through the semiconductor layer, the via being formed such that an inside surface of the via is not doped with the dopant of the second type beyond the depth of the emitter region;
forming a dielectric layer on the rear surface of the semiconductor layer and on an inside surface of the via;
forming a conductive path through the via for collecting current from the front surface, the dielectric layer having a thickness between about 100 nm and 5000 nm to electrically insulate the conductive path from the inside surface of the via;
forming a rear bus bar on the rear of the device to couple the conductive path through the via; and
forming a back contact for the rear surface of the semiconductor layer, the back contact formed through a hole patterned through the dielectric layer.

8. The method of claim 7 , wherein the diffusion region in the semiconductor layer is formed by diffusion from the front surface towards the rear surface, such that the semiconductor layer is doped with the dopant of the second type only to the depth of the emitter region in a vicinity of the via.

9. The method of claim 7 , wherein forming the dielectric layer comprises depositing an oxide layer comprising any one of APCVD oxide, pyrolithic oxide, spin-on oxide, spray-on oxide, dip oxide, a silicon oxide, TiO 2 , TiO 2 deposited by solgel, or Al 2 O 3 /TiO 2 pseudobinary alloys (PBAs).

10. The method of claim 9 , further comprising forming a back side passivation layer over the dielectric layer.

11. The method of claim 10 , wherein the back side passivation layer extends at least part of the way into the via.

12. The method of claim 7 , wherein the dielectric layer is formed to extend over the rear surface around the via without being patterned and aligned to the via.

13. The method of claim 7 , wherein the back contacts are formed by forming holes in the dielectric layer and the passivation layer, and filling the holes with electrically conductive contacting material.

14. The method of claim 7 , further comprising firing the device to create the back contacts.

15. A photovoltaic device manufactured by the method of claim 7 .

16. A photovoltaic device comprising:
a semiconductor layer doped with a bulk dopant of a first type and having an emitter region doped with a dopant of a second type formed only at a front surface configured to receive impinging light, the semiconductor layer further having a rear surface opposite to the front surface;
a via formed through the semiconductor layer, such that an inside surface of the via is not doped with the dopant of the second type beyond the depth of the emitter region, the via having a conductive path formed therethrough and over the inner surface for coupling a front contact to a rear bus bar, the front contact being configured to collect current on the front surface, the rear bus bar being formed on the rear surface; and
a dielectric layer covering the rear surface of the semiconductor layer and further covering an inside surface of the via, the dielectric layer having a thickness between about 100 nm and 5000 nm such that the dielectric layer electrically insulates the inside surface of the via from the conductive path.

17. The device of claim 16 , further comprising a back contact for the rear surface of the semiconductor layer, the back contact extending through the dielectric layer to the semiconductor layer.

18. The device of claim 16 , wherein the dielectric layer extends over the rear surface around the via without being patterned and aligned to the via.

Assignees

• Szlufcik Jozef
• Allebe Christophe
• Dross Frederic
• Beaucarne Guy
• Imec

Inventors

• Szlufcik Jozef
• Allebe Christophe
• Dross Frederic
• Beaucarne Guy

Classifications

• H10F77/219

  Arrangements for electrodes of back-contact photovoltaic cells · CPC title

• H10F77/211

  for photovoltaic cells · CPC title

• H10F77/20

  Electrodes · CPC title

• H10F77/223

  for metallisation wrap-through [MWT] photovoltaic cells · CPC title

• H10F71/121 Primary

  The active layers comprising only Group IV materials · CPC title